ATMEGA8535-16PJ Atmel, ATMEGA8535-16PJ Datasheet - Page 174
![IC MCU AVR 8K 5V 16MHZ 40-DIP](/photos/6/70/67049/453-40-dip_sml.jpg)
ATMEGA8535-16PJ
Manufacturer Part Number
ATMEGA8535-16PJ
Description
IC MCU AVR 8K 5V 16MHZ 40-DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8535-16PJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Two-wire Serial
Interface
Features
Two-wire Serial Interface
Bus Definition
TWI Terminology
174
ATmega8535(L)
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The Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applica-
tions. The TWI protocol allows the systems designer to interconnect up to 128 different
devices using only two bi-directional bus lines, one for clock (SCL) and one for data
(SDA). The only external hardware needed to implement the bus is a single pull-up
resistor for each of the TWI bus lines. All devices connected to the bus have individual
addresses, and mechanisms for resolving bus contention are inherent in the TWI
protocol.
Figure 76. TWI Bus Interconnection
The following definitions are frequently encountered in this section.
Table 73. TWI Terminology
Term
Master
Slave
Transmitter
Receiver
Simple yet Powerful and Flexible Communication Interface, only Two Bus Lines Needed
Both Master and Slave Operation Supported
Device can Operate as Transmitter or Receiver
7-bit Address Space Allows up to 128 Different Slave Addresses
Multi-master Arbitration Support
Up to 400 kHz Data Transfer Speed
Slew-rate Limited Output Drivers
Noise Suppression Circuitry Rejects Spikes on Bus Lines
Fully Programmable Slave Address with General Call Support
Address Recognition Causes Wake-up when AVR is in Sleep Mode
SDA
SCL
Device 1
Description
The device that initiates and terminates a transmission. The Master also
generates the SCL clock.
The device addressed by a Master.
The device placing data on the bus.
The device reading data from the bus.
Device 2
Device 3
........
Device n
V
CC
R1
2502K–AVR–10/06
R2
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