ATMEGA8535-16PJ Atmel, ATMEGA8535-16PJ Datasheet - Page 65
ATMEGA8535-16PJ
Manufacturer Part Number
ATMEGA8535-16PJ
Description
IC MCU AVR 8K 5V 16MHZ 40-DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8535-16PJ
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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2502K–AVR–10/06
(DDD5 set (one)) to serve this function. The OC1A pin is also the output pin for the
PWM mode timer function.
• OC1B – Port D, Bit 4
OC1B, Output Compare Match B output: The PD4 pin can serve as an external output
for the Timer/Counter1 Output Compare B. The pin has to be configured as an output
(DDD4 set (one)) to serve this function. The OC1B pin is also the output pin for the
PWM mode timer function.
• INT1 – Port D, Bit 3
INT1, External Interrupt Source 1: The PD3 pin can serve as an external interrupt
source.
• INT0 – Port D, Bit 2
INT0, External Interrupt Source 0: The PD2 pin can serve as an external interrupt
source.
• TXD – Port D, Bit 1
TXD, Transmit Data (Data output pin for the USART). When the USART Transmitter is
enabled, this pin is configured as an output regardless of the value of DDD1.
• RXD – Port D, Bit 0
RXD, Receive Data (Data input pin for the USART). When the USART Receiver is
enabled this pin is configured as an input regardless of the value of DDD0. When the
USART forces this pin to be an input, the pull-up can still be controlled by the PORTD0
bit.
Table 33 and Table 34 relate the alternate functions of Port D to the overriding signals
shown in Figure 26 on page 57.
Table 33. Overriding Signals for Alternate Functions PD7..PD4
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
PD7/OC2
0
0
0
0
OC2 ENABLE
OC2
0
0
–
–
PD6/ICP1
0
0
0
0
0
0
0
0
ICP1 INPUT
–
PD5/OC1A
0
0
0
0
OC1A ENABLE
OC1A
0
0
–
–
ATmega8535(L)
PD4/OC1B
0
0
0
0
OC1B ENABLE
OC1B
0
0
–
–
65
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