AT90CAN128-16MI Atmel, AT90CAN128-16MI Datasheet - Page 182
![IC MCU AVR FLASH 128K 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90CAN128-16MI
Manufacturer Part Number
AT90CAN128-16MI
Description
IC MCU AVR FLASH 128K 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Quantity
Price
Company:
Part Number:
AT90CAN128-16MI
Manufacturer:
ATMEL
Quantity:
430
Company:
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AT90CAN128-16MI
Manufacturer:
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17.5.2
17.6
182
USART Initialization
AT90CAN32/64/128
Parity Bit Calculation
Figure 17-4. Frame Formats
The frame format used by the USARTn is set by the UCSZn2:0, UPMn1:0 and USBSn bits in
UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing
the setting of any of these bits will corrupt all ongoing communication for both the Receiver and
Transmitter.
The USARTn Character SiZe (UCSZn2:0) bits select the number of data bits in the frame. The
USARTn Parity mode (UPMn1:0) bits enable and set the type of parity bit. The selection
between one or two stop bits is done by the USARTn Stop Bit Select (USBSn) bit. The Receiver
ignores the second stop bit. An FEn (Frame Error) will therefore only be detected in the cases
where the first stop bit is zero.
The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the
result of the exclusive or is inverted. The relation between the parity bit and data bits is as
follows:
If used, the parity bit is located between the last data bit and first stop bit of a serial frame.
The USARTn has to be initialized before any communication can take place. The initialization
process normally consists of setting the baud rate, setting frame format and enabling the Trans-
mitter or the Receiver depending on the usage. For interrupt driven USARTn operation, the
Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the
initialization.
Before doing a re-initialization with changed baud rate or frame format, be sure that there are no
ongoing transmissions during the period the registers are changed. The TXCn flag can be used
to check that the Transmitter has completed all transfers, and the RXCn flag can be used to
St
(n)
P
Sp
IDLE
P
P
d
n
even
odd
(IDLE)
St
Start bit, always low.
Data bits (0 to 8).
Parity bit. Can be odd or even.
Stop bit, always high.
No transfers on the communication line (RxDn or TxDn).
An IDLE line must be high.
Parity bit using even parity
Parity bit using odd parity
Data bit n of the character
P
P
even
0
odd
=
=
1
d
d
n 1
n 1
2
–
–
⊕
⊕
3
…
…
⊕
⊕
4
d
d
FRAME
3
3
[5]
⊕
⊕
d
d
2
2
[6]
⊕
⊕
d
d
[7]
1
1
⊕
⊕
d
d
[8]
0
0
⊕
⊕
[P]
0
1
Sp1 [Sp2]
(St / IDLE)
7679H–CAN–08/08
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