AT90CAN128-16MI Atmel, AT90CAN128-16MI Datasheet - Page 82
![IC MCU AVR FLASH 128K 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
AT90CAN128-16MI
Manufacturer Part Number
AT90CAN128-16MI
Description
IC MCU AVR FLASH 128K 64-QFN
Manufacturer
Atmel
Series
AVR® 90CANr
Specifications of AT90CAN128-16MI
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
AT90CAN128-16MI
Manufacturer:
ATMEL
Quantity:
430
Company:
Part Number:
AT90CAN128-16MI
Manufacturer:
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Quantity:
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82
AT90CAN32/64/128
Table 9-13
shown in
Table 9-13.
Table 9-14.
Note:
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
1. When enabled, the Two-wire Serial Interface enables Slew-Rate controls on the output pins
Figure 9-5 on page
PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between
the AIO outputs shown in the port figure and the digital logic of the TWI module.
and
Overriding Signals for Alternate Functions PD7..PD4
Overriding Signals for Alternate Functions in PD3..PD0
Table 9-14
PD3/INT3/TXD1
TXEN1
0
TXEN1
1
TXEN1
TXD1
0
INT3 ENABLE
INT3 ENABLE
INT3 INPUT
–
PD7/T0
0
0
0
0
0
0
0
0
0
T0 INPUT
–
relates the alternate functions of Port D to the overriding signals
72.
PD6/T1/RXCAN
RXCANEN
PORTD6 • PUD
RXCANEN
0
0
0
0
0
0
T1 INPUT/RXCAN
–
PD2/INT2/RXD1
RXEN1
PORTD2 • PUD
RXEN1
0
0
0
0
INT2 ENABLE
INT2 ENABLE
INT2 INPUT/RXD1
–
PD5/XCK1/TXCAN
TXCANEN +
0
TXCANEN
1
TXCANEN + UMSEL1
(XCK1 OUTPUT •
UMSEL1 • TXCANEN) +
(TXCAN • TXCANEN)
0
0
0
XCK1 INPUT
–
TWEN
SDA INPUT
PD1/INT1/SDA
PORTD1 • PUD
0
0
TWEN
SDA_OUT
0
INT1 ENABLE
INT1 ENABLE
INT1 INPUT
(1)
PD0/INT0/SCL
TWEN
PORTD0 • PUD
0
0
TWEN
SCL_OUT
0
INT0 ENABLE
INT0 ENABLE
INT0 INPUT
SCL INPUT
PD4/ICP1
0
0
0
0
0
0
0
0
0
ICP1 INPUT
–
7679H–CAN–08/08
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