AT91SAM7A1-AU Atmel, AT91SAM7A1-AU Datasheet - Page 25

• Manufacturer Part Number: AT91SAM7A1-AU
• Description: IC ARM7 MCU 32BIT ROMLESS144LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7A1-AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 49
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: AT91SAM7A1-EK - BOARD EVAL FOR AT91SAM7A1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9.1
9.1.1
6048B–ATARM–29-Jun-06
Multiplexed I/O Lines
Output Selection
Table 9-1.
Each PIO block in the peripheral is controlled through the peripheral interface. The PIO block
clock is enabled/disabled by the peripheral Power Management Controller (see
page
All I/O lines are multiplexed with an I/O signal of the peripheral. After reset, the pin is con-
trolled by the peripheral PIO controller. When a peripheral signal is not used in an application,
the corresponding pin can be used as a parallel I/O.
Each parallel I/O line is bi-directional, whether the peripheral defines the signal as input or
output.
Figure 9-1 on page 24
signal.
Each pin of the peripheral can be independently controlled using the Peripheral_PER (PIO
Enable) and Peripheral_PDR (PIO Disable) registers.
The Peripheral_PSR (PIO Status) indicates whether the pin is controlled by the peripheral or
by the PIO controller block.
The user can select the direction of each individual I/O signal (input or output) using the
Peripheral_OER (Output Enable) and Peripheral_ODR (Output Disable) registers. The output
status of the I/O signal can be read in the Peripheral_OSR (Output Status) register. The direc-
tion defined has effect only if the pin is configured to be controlled by the PIO controller block.
Module
SPI
ADC0
GPT0 TC0
GPT0 TC1
GPT0 TC2
PWM
CAN
UPIO
CAPT0
CAPT1
Simple Timer ST0
Simple Timer ST1
CM
PMC
PDC
GIC
22).
PIO Block Multiplexing (Continued)
PIO Block
shows the multiplexing of the peripheral signals with the PIO controller
Present
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
Number of MPIO
18
4
7
3
3
3
1
1
-
-
-
-
-
-
-
-
Name of PIO Lines
MISO, MOSI, SPCK, NPCS[3:0]
-
TIOA0, TIOB0, TCLK0
TIOA1, TIOB1, TCLK1
TIOA2, TIOB2, TCLK2
PWM[3:0]
-
UPIO[17:0]
CAPT0
CAPT1
-
-
-
-
-
-
AT91SAM7A1
Table 7-4 on
25