ATMEGA3290-16AI Atmel, ATMEGA3290-16AI Datasheet - Page 239

• Manufacturer Part Number: ATMEGA3290-16AI
• Description: IC AVR MCU 32K 16MHZ 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA3290-16AI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATSTK504 - STARTER KIT AVR EXP MOD 100P LCD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

23.4
23.4.1
23.4.2
2552K–AVR–04/11
Register Description
LCDCRA – LCD Control and Status Register A
LCDCRB – LCD Control and Status Register B
• Bit 7 – LCDEN: LCD Enable
Writing this bit to one enables the LCD Controller/Driver. By writing it to zero, the LCD is turned
off immediately. Turning the LCD Controller/Driver off while driving a display, enables ordinary
port function, and DC voltage can be applied to the display if ports are configured as output. It is
recommended to drive output to ground if the LCD Controller/Driver is disabled to discharge the
display.
• Bit 6 – LCDAB: LCD Low Power Waveform
When LCDAB is written logic zero, the default waveform is output on the LCD pins. When
LCDAB is written logic one, the Low Power Waveform is output on the LCD pins. If this bit is
modified during display operation the change takes place at the beginning of a new frame.
• Bit 5 – Reserved Bit
This bit is reserved bit in the ATmega329/3290/649/6490 and will always read as zero.
• Bit 4 – LCDIF: LCD Interrupt Flag
This bit is set by hardware at the beginning of a new frame, at the same time as the display data
is updated. The LCD Start of Frame Interrupt is executed if the LCDIE bit and the I-bit in SREG
are set. LCDIF is cleared by hardware when executing the corresponding Interrupt Handling
Vector. Alternatively, writing a logical one to the flag clears LCDIF. Beware that if doing a Read-
Modify-Write on LCDCRA, a pending interrupt can be disabled. If Low Power Waveform is
selected the Interrupt Flag is set every second frame.
• Bit 3 – LCDIE: LCD Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the LCD Start of Frame Interrupt is
enabled.
• Bits 2:1 – Reserved Bits
These bits are reserved bits in the ATmega329/3290/649/6490 and will always read as zero.
• Bit 0 – LCDBL: LCD Blanking
When this bit is written to one, the display will be blanked after completion of a frame. All seg-
ment and common pins will be driven to ground.
Note:
Bit
(0xE4)
Read/Write
Initial Value
Bit
(0xE5)
Read/Write
Initial Val-
ue
Bit 3, LCDPM3 is only available in ATmega3290/6490.
LCDCS
R/W
LCDEN
7
0
R/W
7
0
LCD2B
R/W
6
0
LCDAB
R/W
6
0
LCDMUX1
R/W
5
0
R
5
–
0
LCDMUX0
LCDIF
R/W
R/W
4
0
4
0
ATmega329/3290/649/6490
LCDPM3
LCDIE
R/W
R/W
3
0
3
0
LCDPM2
R/W
R
2
–
0
2
0
LCDPM1
R
1
–
0
R/W
1
0
LCDBL
R/W
LCDPM0
0
0
R/W
0
0
LCDCRA
LCDCRB
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