ATTINY2313V-10SI Atmel, ATTINY2313V-10SI Datasheet - Page 10
![IC AVR MCU FLASH 2K 1.8V 20SOIC](/photos/6/80/68042/453-20-soic_sml.jpg)
ATTINY2313V-10SI
Manufacturer Part Number
ATTINY2313V-10SI
Description
IC AVR MCU FLASH 2K 1.8V 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY2313V-10SI
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY2313V-10SI
Manufacturer:
ATMEL
Quantity:
560
Part Number:
ATTINY2313V-10SI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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The X-register, Y-
register, and Z-register
10
ATtiny2313
Figure 4. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in
directly into the first 32 locations of the user Data Space. Although not being physically imple-
mented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
The registers R26..R31 have some added functions to their general purpose usage. These reg-
isters are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in
Figure 5. The X-, Y-, and Z-registers
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
X-register
Y-register
Z-register
Registers
Purpose
Working
General
Figure
15
7
R27 (0x1B)
15
7
R29 (0x1D)
15
7
R31 (0x1F)
4, each register is also assigned a data memory address, mapping them
7
XH
YH
ZH
0
R13
R14
R15
R16
R17
R26
R27
R28
R29
R30
R31
R0
R1
R2
…
…
0
0
0
7
R26 (0x1A)
7
R28 (0x1C)
7
R30 (0x1E)
Addr.
0x0D
0x0E
0x0F
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x00
0x01
0x02
0x10
0x11
Figure
5.
X-register High Byte
Y-register High Byte
Z-register High Byte
X-register Low Byte
Y-register Low Byte
Z-register Low Byte
XL
YL
ZL
0
2543L–AVR–08/10
0
0
0
0
0
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