ATTINY2313V-10SI Atmel, ATTINY2313V-10SI Datasheet - Page 140
![IC AVR MCU FLASH 2K 1.8V 20SOIC](/photos/6/80/68042/453-20-soic_sml.jpg)
ATTINY2313V-10SI
Manufacturer Part Number
ATTINY2313V-10SI
Description
IC AVR MCU FLASH 2K 1.8V 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY2313V-10SI
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
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SPI Master Operation
Example
140
ATtiny2313
The Three-wire mode timing is shown in Figure 62. At the top of the figure is a USCK cycle refer-
ence. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The USCK
timing is shown for both external clock modes. In External Clock mode 0 (USICS0 = 0), DI is
sampled at positive edges, and DO is changed (data register is shifted by one) at negative
edges. External Clock mode 1 (USICS0 = 1) uses the opposite edges versus mode 0, i.e., sam-
ples data at negative and changes the output at positive edges. The USI clock modes
corresponds to the SPI data mode 0 and 1.
Referring to the timing diagram (Figure 62.), a bus transfer involves the following steps:
1. The Slave device and Master device sets up its data output and, depending on the proto-
2. The Master generates a clock pulse by software toggling the USCK line twice (C and D).
3. Step 2. is repeated eight times for a complete register (byte) transfer.
4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that
The following code demonstrates how to use the USI module as a SPI Master:
The code is size optimized using only eight instructions (+ ret). The code example assumes that
the DO and USCK pins are enabled as output in the DDRB Register. The value stored in register
r16 prior to the function is called is transferred to the Slave device, and when the transfer is com-
pleted the data received from the Slave is stored back into the r16 Register.
The second and third instructions clears the USI Counter Overflow Flag and the USI counter
value. The fourth and fifth instruction set Three-wire mode, positive edge Shift Register clock,
count at USITC strobe, and toggle USCK. The loop is repeated 16 times.
col used, enables its output driver (mark A and B). The output is set up by writing the
data to be transmitted to the Serial Data Register. Enabling of the output is done by set-
ting the corresponding bit in the port Data Direction Register. Note that point A and B
does not have any specific order, but both must be at least one half USCK cycle before
point C where the data is sampled. This must be done to ensure that the data setup
requirement is satisfied. The 4-bit counter is reset to zero.
The bit value on the slave and master’s data input (DI) pin is sampled by the USI on the
first edge (C), and the data output is changed on the opposite edge (D). The 4-bit counter
will count both edges.
the transfer is completed. The data bytes transferred must now be processed before a
new transfer can be initiated. The overflow interrupt will wake up the processor if it is set
to Idle mode. Depending of the protocol used the slave device can now set its output to
high impedance.
SPITransfer:
SPITransfer_loop:
out
ldi
out
ldi
out
sbis
rjmp
in
ret
USIDR,r16
r16,(1<<USIOIF)
USISR,r16
r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC)
USICR,r16
USISR,USIOIF
SPITransfer_loop
r16,USIDR
2543L–AVR–08/10
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