ATTINY2313V-10SI Atmel, ATTINY2313V-10SI Datasheet - Page 60
![IC AVR MCU FLASH 2K 1.8V 20SOIC](/photos/6/80/68042/453-20-soic_sml.jpg)
ATTINY2313V-10SI
Manufacturer Part Number
ATTINY2313V-10SI
Description
IC AVR MCU FLASH 2K 1.8V 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY2313V-10SI
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
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General Interrupt
Mask Register –
GIMSK
60
ATtiny2313
• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT1 pin that activate the
interrupt are defined in
If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt.
Table 31. Interrupt 1 Sense Control
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt.
Table 32. Interrupt 0 Sense Control
• Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU
Control Register – MCUCR – define whether the external interrupt is activated on rising and/or
falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request
even if INT1 is configured as an output. The corresponding interrupt of External Interrupt
Request 1 is executed from the INT1 Interrupt Vector.
• Bit 6 – INT0: External Interrupt Request 0 Enable
Read/Write
Initial Value
Bit
Read/Write
Initial Value
ISC01
ISC11
0
0
1
1
0
0
1
1
ISC10
ISC00
INT1
R/W
R/W
0
7
0
0
1
0
1
0
1
0
1
R/W
INT0
R/W
Table
Table
Description
The low level of INT1 generates an interrupt request.
Any logical change on INT1 generates an interrupt request.
The falling edge of INT1 generates an interrupt request.
The rising edge of INT1 generates an interrupt request.
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
0
6
0
32. The value on the INT1 pin is sampled before detecting edges.
32. The value on the INT0 pin is sampled before detecting edges.
R/W
PCIE
R/W
0
5
0
R/W
0
R
4
–
0
R/W
0
R
3
–
0
R/W
0
R
2
–
0
R/W
0
R
1
–
0
R/W
0
R
0
–
0
GIMSK
2543L–AVR–08/10
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