ATTINY44-20SSU Atmel, ATTINY44-20SSU Datasheet - Page 15

IC MCU AVR 4K FLASH 20MHZ 14SOIC

ATTINY44-20SSU

Manufacturer Part Number
ATTINY44-20SSU
Description
IC MCU AVR 4K FLASH 20MHZ 14SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheets

Specifications of ATTINY44-20SSU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Cpu Family
ATtiny
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
SPI/USI
Total Internal Ram Size
256Byte
# I/os (max)
12
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
14
Package Type
SOIC
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
5. Memories
5.1
5.2
8006K–AVR–10/10
In-System Re-programmable Flash Program Memory
SRAM Data Memory
This section describes the different memories in the ATtiny24/44/84. The AVR architecture has
two main memory spaces, the Data memory and the Program memory space. In addition, the
ATtiny24/44/84 features an EEPROM Memory for data storage. All three memory spaces are lin-
ear and regular.
The ATtiny24/44/84 contains 2/4/8K byte On-chip In-System Reprogrammable Flash memory
for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as
1024/2048/4096 x 16.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny24/44/84
Program Counter (PC) is 10/11/12 bits wide, thus addressing the 1024/2048/4096 Program
memory locations.
data serial downloading using the SPI pins.
Constant tables can be allocated within the entire Program memory address space (see instruc-
tions LPM – Load Program Memory and SPM – Store Program Memory).
Timing diagrams for instruction fetch and execution are presented in
ing” on page
Figure 5-1.
Figure 5-2 on page 16
The lower data memory locations address both the Register File, the I/O memory and the inter-
nal data SRAM. The first 32 locations address the Register File, the next 64 locations the
standard I/O memory, and the last 128/256/512 locations address the internal data SRAM.
The five different addressing modes for the Data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
12.
Program Memory Map
“Memory Programming” on page 159
shows how the ATtiny24/44/84 SRAM Memory is organized.
Program Memory
0x03FF/0x07FF/0xFFF
0x0000
contains a detailed description on Flash
ATtiny24/44/84
“Instruction Execution Tim-
15

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