ATMEGA169P-16MCU Atmel, ATMEGA169P-16MCU Datasheet - Page 63
ATMEGA169P-16MCU
Manufacturer Part Number
ATMEGA169P-16MCU
Description
MCU AVR 16K ISP FLSH 16MHZ 64QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA169PV-8AU.pdf
(395 pages)
Specifications of ATMEGA169P-16MCU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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12.2.3
12.2.4
8018P–AVR–08/10
EIFR – External Interrupt Flag Register
PCMSK1 – Pin Change Mask Register 1
interrupt request even if INT0 is configured as an output. The corresponding interrupt of External
Interrupt Request 0 is executed from the INT0 Interrupt Vector.
• Bit 7 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 6 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7:0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set
(one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
• Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15..8
Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT15..8 is cleared, pin change interrupt on the corresponding I/O
pin is disabled.
Bit
0x1C (0x3C)
Read/Write
Initial Value
Bit
(0x6C)
Read/Write
Initial Value
PCINT15
PCIF1
R/W
R/W
7
0
7
0
PCINT14
PCIF0
R/W
R/W
6
0
6
0
PCINT13
R/W
R
5
–
0
5
0
PCINT12
R/W
R
4
–
0
4
0
PCINT11
R/W
R
3
–
0
3
0
PCINT10
R/W
2
–
R
0
2
0
PCINT9
ATmega169P
R/W
R
1
–
0
1
0
PCINT8
INTF0
R/W
R/W
0
0
0
0
PCMSK1
EIFR
63
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