ATMEGA88PA-MU Atmel, ATMEGA88PA-MU Datasheet - Page 26

• Manufacturer Part Number: ATMEGA88PA-MU
• Description: MCU AVR 8K ISP FLASH MEM 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA88PA-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Rohs Compliant: Yes
• Package: 32QFN EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 23
• Interface Type: SPI/TWI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8. System Clock and Clock Options
8.1
8.1.1
8.1.2
8271C–AVR–08/10
Clock Systems and their Distribution
CPU Clock – clk
I/O Clock – clk
I/O
Figure 8-1
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in
ment and Sleep Modes” on page
Figure 8-1.
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.
The I/O clock is also used by the External Interrupt module, but note that start condition detec-
tion in the USI module is carried out asynchronously when clk
recognition in all sleep modes.
Note:
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
CPU
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the
level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt
will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described in
”System Clock and Clock Options” on page
Asynchronous
Timer/Counter
Timer/Counter
Oscillator
presents the principal clock systems in the AVR and their distribution. All of the clocks
Clock Distribution
General I/O
Modules
External Clock
clk
clk
ASY
I/O
39. The clock systems are detailed below.
System Clock
Control Unit
AVR Clock
Multiplexer
Prescaler
Clock
ADC
clk
Source clock
Oscillator
ADC
Crystal
26.
CPU Core
clk
clk
Reset Logic
CPU
FLASH
Crystal Oscillator
Watchdog clock
Low-frequency
Watchdog Timer
RAM
I/O
Watchdog
Oscillator
is halted, TWI address
Calibrated RC
”Power Manage-
Flash and
EEPROM
Oscillator
26