AT91FR40162SB-CU-999 Atmel, AT91FR40162SB-CU-999 Datasheet
AT91FR40162SB-CU-999
Specifications of AT91FR40162SB-CU-999
Available stocks
Related parts for AT91FR40162SB-CU-999
AT91FR40162SB-CU-999 Summary of contents
Page 1
... I/O Operating Range, 1.65V to 1.95V Core Operating Range • -40⋅ 85⋅ C Temperature Range • Available in a 121-ball 1.26 mm BGA Package with 0.8 mm Ball Pitch ® ® Thumb Processor Core AT91 ARM Thumb-based Microcontrollers AT91FR40162SB Preliminary 6410B–ATARM–12-Jan-10 ...
Page 2
... The AT91FR40162SB is pin-to-pin compatible to the AT91FR40162S, so the AT91FR40162SB can be soldered in place of the AT91FR40162S without any other hardware changes. The AT91FR40162SB does not feature a VPP pin, thus ball D5 of the 121-ball BGA package of the AT91FR40162SB is NC (Not connected). This ball can either be connected to a supply up to 13V (as could be the VPP ball of the AT91FR40162S), grounded or left unconnected ...
Page 3
... Users who managed the programming of the flash with the CFI algorithm on the AT91FR40162S should adapt their programming for the AT91FR40162SB. 2.3.5 Fully Green Package The AT91FR40162S is RoHS compliant, whereas the AT91FR40162SB is fully Green qualified. This has no impact on the soldering profile to be used, but only improves environmental considerations. 6410B–ATARM–12-Jan-10 AT91FR40162SB (Table 12-5, “ ...
Page 4
... Pin Configuration Figure 3-1. AT91FR40162SB Pinout for 121-ball BGA Package (Top View) A1 Corner 1 2 P21/TXD1 P19 NTRI P22 P20 RXD1 SCK1 VDDIO GND P23 MCKI P24 P25 NWDOVF BMS MCK0 GND TMS NWE TDO NWR0 P26 VDDCORE VDDIO NCS2 NWAIT GND ...
Page 5
... Signal Description Table 4-1. AT91FR40162SB Signal Description Module Name Function A0 - A23 Address Bus D0 - D15 Data Bus NCS0 - NCS3 External Chip Select CS4 - CS7 External Chip Select NWR0 Lower Byte 0 Write Signal NWR1 Upper Byte 1 Write Signal NRD Read Signal EBI NWE ...
Page 6
... Table 4-1. AT91FR40162SB Signal Description (Continued) Module Name Function NCSF Flash Memory Select Flash NBUSY Flash Memory Busy Output Memory NRSTF Flash Memory Reset Input VDDIO Power Power VDDCORE Power GND Ground AT91FR40162SB 6 Active Type Level Comments Input Low Enables Flash Memory when pulled low ...
Page 7
... Block Diagram Figure 5-1. 6410B–ATARM–12-Jan-10 AT91FR40162SB Block Diagram Interface Bus External EBI: AT91FR40162SB 7 ...
Page 8
... Memories The AT91FR40162SB embeds 256K bytes of internal SRAM. The internal memory is directly connected to the 32-bit data bus and is single-cycle accessible. This provides maximum perfor- mance of 67 MIPS at 75 MHz by using the ARM instruction set of the processor, minimizing system power consumption and improving on the performance of separate memory solutions ...
Page 9
... Peripheral Data Controller (PDC) channels. The 3-channel, 16-bit Timer Counter (TC) is highly programmable and supports capture or waveform modes. Each TC channel can be programmed to measure or generate different kinds of waves, and can detect and control two input/output signals. The TC has also 3 external clock signals. 6410B–ATARM–12-Jan-10 AT91FR40162SB 9 ...
Page 10
... Master Clock The AT91FR40162SB has a fully static design and works on the Master Clock (MCK), provided on the MCKI pin from an external source. The Master Clock is also provided as an output of the device on the pin MCKO, which is multi- plexed with a general purpose I/O line ...
Page 11
... Tri-state Mode The AT91FR40162SB microcontroller provides a tri-state mode, which is used for debug pur- poses. This enables the connection of an emulator probe to an application board without having to desolder the device from the target board. In tri-state mode, all the output pin drivers of the AT91R40008 microcontroller are disabled ...
Page 12
... In any of these address spaces, the ARM7TDMI operates in little-endian mode only. 7.6.1 Internal Memories The AT91FR40162SB microcontroller integrates 256K bytes of internal SRAM bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) and word (32-bit) accesses are supported and are executed within one cycle. Fetching either Thumb or ARM instructions is sup- ported, and internal memory can store two times as many Thumb instructions as ARM instructions ...
Page 13
... AT91FR40162SB uses a remap command that enables switching between the boot memory and the internal primary SRAM bank addresses. The remap command is accessible through the EBI User Interface by writing one in RCB of EBI_RCR (Remap Control Register). Performing a remap command is mandatory if access to the other external devices (connected to chip selects required ...
Page 14
... Program Inhibit – holding any one of OE low, CE high or WE high inhibits program cycles. • Noise Filter – pulses of less than a certain duration on the inputs will not initiate a program cycle. AT91FR40162SB 14 6410B–ATARM–12-Jan-10 ...
Page 15
... Flash Memory Uploader Operations The Flash Memory Uplo ader requires the encapsulated Flash to be used as the AT91FR40162SB boot memory and a valid clock to be applied to MCKI. After reset, the Flash Memory Uploader immediately recopies itself into the internal SRAM and jumps to it. The follow- ing operation requires this memory resource only ...
Page 16
... Note that in the event that the Flash Memory Uploader is erased from the first sector while the new final application is not yet programmed, and while the target system power supply is switched off, it leads to a non-recoverable error and the AT91FR40162SB cannot be re-pro- grammed by using the Flash Memory Uploader. ...
Page 17
... Peripheral Data Controller The AT91FR40162SB has a 4-channel PDC dedicated to the two on-chip USARTs. One PDC channel is dedicated to the receiver and one to the transmitter of each USART. The user interface of a PDC channel is integrated in the memory space of each USART. It con- tains a 32-bit Address Pointer Register (RPR or TPR) and a 16-bit Transfer Counter Register (RCR or TCR) ...
Page 18
... PIO: Parallel I/O Controller The AT91FR40162SB has 32 programmable I/O lines. Six pins are dedicated as general-pur- pose I/O pins. Other I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins. The PIO controller enables generation of an interrupt on input change and insertion of a simple input glitch filter on any of the PIO pins ...
Page 19
... TC: Timer Counter The AT91FR40162SB features a Timer Counter block that includes three identical 16-bit timer counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse gen- eration, delay timing and pulse width modulation. ...
Page 20
... Memory Map Figure 9-1. AT91FR40162SB Memory Map Before and After the Remap Command Before Address Function Size 0xFFFFFFFF On-chip 4M Bytes Peripherals 0xFFC00000 0xFFBFFFFF Reserved 0x00400000 0x003FFFFF On-chip 1M Byte Primary RAM Bank 0x00300000 0x002FFFFF Reserved 1M Byte On-chip Device 0x00200000 0x001FFFFF Reserved 1M Byte ...
Page 21
... Timer Counter TC Reserved Universal Synchronous/ USART0 Asynchronous Receiver/Transmitter 0 Universal Synchronous/ USART1 Asynchronous Receiver/Transmitter 1 Reserved SF Special Function Reserved EBI External Bus Interface Reserved AT91FR40162SB Size 4K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 21 ...
Page 22
... If two chip selects are defined as having the same base address, an access to the overlapping address space asserts both NCS lines. The Chip Select Register with the smaller number defines the characteristics of the external access and the behavior of the control signals. AT91FR40162SB 22 describes the EBI User Interface. ...
Page 23
... Upper and lower byte select (output) Wait request (input) Functions Allows from chip select lines to be used 8- or 16-bit data bus Byte write or byte select access Byte write or byte select access Byte write or byte select access AT91FR40162SB Base + 4M Bytes Hi Repeat 3 Low Base + 3M Bytes Hi Repeat 2 ...
Page 24
... EBI Note: Figure 11-3. Memory Connections for Eight External Devices CS4 - CS7 NCS0 - NCS3 NRD EBI NWRx A0 - A19 D0 - D15 Note: AT91FR40162SB 24 NCS0 - NCS3 NRD NWRx A0 - A23 D0 - D15 For four external devices, the maximum address space per device is 16M bytes. NCS1 NCS0 For eight external devices, the maximum address space per device is 1M byte ...
Page 25
... NWR1 NWR0 NRD NCS2 shows how to connect a 512K x 16-bit memory on NCS2 D15 A1 - A19 EBI NLB NUB NWE NOE NCS2 AT91FR40162SB A18 A0 Write Enable Output Enable Memory Enable D15 A0 - A18 Low Byte Enable High Byte Enable Write Enable Output Enable Memory Enable ...
Page 26
... The signal NWR1/NUB is used as NUB and enables the upper byte for both read and write operations. • The signal NWR0/NWE is used as NWE and enables writing for byte or half word. • The signal NRD/NOE is used as NOE and enables reading for byte or half word. AT91FR40162SB 26 shows how to connect two 512K x 8-bit devices in parallel on NCS2 ...
Page 27
... NWE NOE NCS2 shows how to connect a 16-bit device without byte access (e.g. Flash) on NCS2 D15 A1 - A19 EBI NLB NUB NWE NOE NCS2 AT91FR40162SB D15 A0 - A18 Low Byte Enable High Byte Enable Write Enable Output Enable Memory Enable D15 A0 - A18 Write Enable ...
Page 28
... AT91FR40162SB 28 In the following waveforms and descriptions, NRD represents NRD and NOE since the two signals have the same waveform ...
Page 29
... Early read wait states affect the external bus only. They do not affect internal bus timing. Figure 11-9. Standard Read Protocol Figure 11-10. Early Read Protocol 6410B–ATARM–12-Jan-10 MCKI ADDR NCS NRD or NWE MCKI ADDR NCS NRD or NWE AT91FR40162SB 29 ...
Page 30
... Figure 11-12. Data Hold Time In early read protocol the data can remain valid longer than in standard read protocol due to the additional wait cycle which follows a write access. AT91FR40162SB 30 Write Cycle Early Read Wait ...
Page 31
... Section 11.7 “Read Protocols” on page 1/2 cycle 1 cycle 1 Wait State Access MCK ADDR NCS NWE NRD (2) (1) 1. Early Read Protocol 2. Standard Read Protocol ) for each external memory device is programmed in the TDF DF AT91FR40162SB 28) 31 ...
Page 32
... When NWAIT is de-asserted, the EBI finishes the access sequence. The NWAIT signal must meet setup and hold requirements on the rising edge of the clock. AT91FR40162SB 32 will not slow down the execution of a program from internal ...
Page 33
... Figure 11-16. Chip Select Wait Notes: 6410B–ATARM–12-Jan-10 MCK ADDR NWAIT NCS NWE NRD (2) (1) 1. Early Read Protocol 2. Standard Read Protocol Mem 1 MCK NCS1 NCS2 NRD (1) (2) NWE 1. Early Read Protocol 2. Standard Read Protocol AT91FR40162SB Chip Select Wait Mem 2 33 ...
Page 34
... Memory Access Waveforms Figure 11-17 memory read access. Figure 11-17. Standard Read Protocol without t AT91FR40162SB 34 through show examples of the two alternative protocols for external Figure 11-20 DF 6410B–ATARM–12-Jan-10 ...
Page 35
... Figure 11-18. Early Read Protocol Without t 6410B–ATARM–12-Jan-10 AT91FR40162SB DF 35 ...
Page 36
... Figure 11-19. Standard Read Protocol with t AT91FR40162SB 36 DF 6410B–ATARM–12-Jan-10 ...
Page 37
... Figure 11-20. Early Read Protocol With t 6410B–ATARM–12-Jan-10 AT91FR40162SB DF 37 ...
Page 38
... Figure 11-21 access to the various AT91FR40162SB external memory devices. The configurations described are shown in the following table: Table 11-3. Figure Number Figure 11-21 Figure 11-22 Figure 11-23 Figure 11-24 Figure 11-25 Figure 11-26 Figure 11-27 AT91FR40162SB 38 through show the timing cycles and wait states for read and write ...
Page 39
... Figure 11-21. 0 Wait States, 16-bit Bus Width, Word Transfer MCK A1 - A23 NCS NLB NUB READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS · Byte Write/ Byte Select Option NWE D0 - D15 6410B–ATARM–12-Jan-10 ADDR ADDR AT91FR40162SB ...
Page 40
... Figure 11-22. 1 Wait, 16-bit Bus Width, Word Transfer MCK A1 - A23 NCS NLB NUB READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS · Byte Write/ Byte Select Option NWE D0 - D15 AT91FR40162SB 40 1 Wait State ADDR Wair State ADDR ...
Page 41
... Figure 11-23. 1 Wait State, 16-bit Bus Width, Half-word Transfer MCK A1 - A23 READ ACCESS · Standard Protocol D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS · Byte Write/ Byte Select Option NWE D0 - D15 6410B–ATARM–12-Jan-10 1 Wait State NCS NLB NUB NRD AT91FR40162SB ...
Page 42
... Figure 11-24. 0 Wait States, 8-bit Bus Width, Word Transfer MCK A0 - A23 NCS READ ACCESS · Standard Protocol NRD D0-D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS NWR0 NWR1 D0 - D15 AT91FR40162SB 42 ADDR ADDR ADDR+2 ADDR 6410B–ATARM–12-Jan- ...
Page 43
... Figure 11-25. 1 Wait State, 8-bit Bus Width, Half-word Transfer 1 Wait State MCK A0 - A23 NCS READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS NWR0 NWR1 D0 - D15 6410B–ATARM–12-Jan-10 1 Wait State ADDR AT91FR40162SB ADDR ...
Page 44
... Figure 11-26. 1 Wait State, 8-bit Bus Width, Byte Transfer MCK A0 - A23 NCS READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS NWR0 NWR1 D0 - D15 AT91FR40162SB 44 1 Wait State 6410B–ATARM–12-Jan-10 ...
Page 45
... Internal Address NCS NLB NUB READ ACCESS · Standard Protocol NRD D0 - D15 Internal Bus · Early Protocol NRD D0 - D15 WRITE ACCESS · Byte Write Option NWR0 NWR1 D0 - D15 · Byte Select Option NWE 6410B–ATARM–12-Jan-10 ADDR ADDR AT91FR40162SB ADDR ADDR ...
Page 46
... Chip Select Register 6 0x1C Chip Select Register 7 0x20 Remap Control Register 0x24 Memory Control Register Notes: 1. 8-bit boot (if BMS is detected high) 2. 16-bit boot (if BMS is detected low) AT91FR40162SB 46 (See “Boot on NCS0” on page Name Access EBI_CSR0 Read/Write EBI_CSR1 Read/Write EBI_CSR2 Read/Write ...
Page 47
... CSEN BAT 5 4 WSE NWS Data Bus Width Reserved 16-bit data bus width 8-bit data bus width Reserved Number of Standard Wait States AT91FR40162SB – – – TDF Code Label EBI_DBW – EBI_DBW_16 EBI_DBW_8 – Code Label EBI_NWS EBI_NWS_1 EBI_NWS_2 EBI_NWS_3 ...
Page 48
... Chip select is enabled. • BA: Base Address (Code Label EBI_BA) These bits contain the highest bits of the base address. If the page size is larger than 1M byte, the unused bits of the base address are ignored by the EBI decoder. AT91FR40162SB 48 Active Bits in Base Address 12 Bits (31 - 20) ...
Page 49
... RCB: Remap Command Bit (Code Label EBI_RCB effect Cancels the remapping (performed at reset) of the page zero memory devices. 6410B–ATARM–12-Jan- – – – – – – – – – – – – AT91FR40162SB – – – – – – – – – – – RCB 49 ...
Page 50
... A20, A21, A22 A20, A21 A20 None • DRP: Data Read Protocol DRP Selected DRP 0 Standard read protocol for all external memory devices enabled 1 Early read protocol for all external memory devices enabled AT91FR40162SB – – – – – – – – – ...
Page 51
... If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O pins I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tri-stated, and the I/O15 pin is used as an input for the LSB (A-1) address function. 6410B–ATARM–12-Jan-10 “Sector Lockdown” on page 55). AT91FR40162SB 51 ...
Page 52
... low (respectively) and OE high. The address is latched on the falling edge WE, whichever occurs last. The data is latched by the first rising edge WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. AT91FR40162SB 52 I/O0 - I/O15/A-1 Output ...
Page 53
... The configuration register can be set to one of two different val- 6410B–ATARM–12-Jan-10 . When the sector programming lockdown feature is not SEC “Status Bit Table” on page 62 and the following four sections describe AT91FR40162SB . EC cycle time. The BP 53 ...
Page 54
... Product ID Exit com- mand to return to the read mode. The erase/program status bit is a “0” while the erase or program operation is still in progress. Please see AT91FR40162SB 54 Table 12-2, “Command Definition Table,” on page ...
Page 55
... The command sequence for the erase sus- pend and program suspend are the same, and the command sequence for the erase resume and program resume are the same. 6410B–ATARM–12-Jan-10 and Section 12.9 “Software Product Identification Exit” on page AT91FR40162SB Section 12.8 ”Software Product 66), a read 55 ...
Page 56
... Hardware Data Protection The Hardware Data Protection feature protects against inadvertent programs to the Flash Mem- ory in the following ways: (a) V inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. AT91FR40162SB 56 “Software Product Identification Entry” 66. for more details. ...
Page 57
... Input Levels While operating with a 2.65V to 3.6V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 6410B–ATARM–12-Jan-10 AT91FR40162SB + 0.6V ...
Page 58
... Figure 12-2. Data Polling Algorithm (Configuration Register = 00) Notes: AT91FR40162SB 58 START Read I/O7 - I/O0 Addr = VA I/O7 = Data I/ YES Read I/O7 - I/O0 Addr = VA I/O7 = Data? NO Program/Erase Operation Not Successful, Write Product ID Exit Command Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased ...
Page 59
... VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non- protected sector address. 2. I/O7 should be rechecked even if I/O5 = “1” because I/O7 may change simultaneously with I/O5. AT91FR40162SB YES YES Program/Erase Operation ...
Page 60
... Figure 12-4. Toggle Bit Algorithm (Configuration Register = 00) Note: AT91FR40162SB 60 START Read I/O7 - I/O0 Read I/O7 - I/O0 Toggle Bit = Toggle? YES NO I/ YES Read I/O7 - I/O0 Twice Toggle Bit = Toggle? YES Program/Erase Operation Not Successful, Write Product ID Exit Command The system should recheck the toggle bit even if I/O5 = “1” because the toggle bit may stop tog- gling as I/O5 changes to “ ...
Page 61
... YES Program/Erase Operation Not Successful, Write Product ID Exit Command The system should recheck the toggle bit even if I/O5 = “1” because the toggle bit may stop tog- gling as I/O5 changes to “1”. AT91FR40162SB NO NO Program/Erase Operation Successful, Write Product ID Exit Command ...
Page 62
... Program Suspended & Read Programming Sector Program Suspended & Read Non-programming Sector Note: 1. I/O5 switches to a “1” when a program or an erase operation has exceeded the maximum time limits or when a program or sector erase operation is performed on a protected sector. AT91FR40162SB 62 I/O7 I/O7 I/ ...
Page 63
... AA AAA 55 555 F0 ( AAA 55 555 C0 AA AAA 55 555 C0 AA AAA 55 555 90 AA AAA 55 555 D0 98 for details). AT91FR40162SB 4th Bus 5th Bus Cycle Cycle Addr Data Addr Data 555 AA AAA 55 555 AA AAA 55 Addr D IN 555 AA AAA 55 555 AA AAA 55 (10) Addr D IN ...
Page 64
... Protection Register Addressing Table 12-3. Protection Register Addressing Table Word Use Block 0 Factory 1 Factory 2 Factory 3 Factory 4 User 5 User 6 User 7 User Note: 1. All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A19 - AT91FR40162SB 64 ( ...
Page 65
... AT91FR40162SB x16 Address Range (A19 - A0) 00000 - 00FFF 01000 - 01FFF 02000 - 02FFF 03000 - 03FFF 04000 - 04FFF 05000 - 05FFF 06000 - 06FFF 07000 - 07FFF ...
Page 66
... Software Product Identification Entry Figure 12-6. 12.9 Software Product Identification Exit Figure 12-7. Notes: AT91FR40162SB 66 Software Product Identification Entry LOAD DATA AA ENTER PRODUCT IDENTIFICATION Software Product Identification Exit LOAD DATA AA TO ADDRESS 555 LOAD DATA 55 TO ADDRESS AAA LOAD DATA F0 ...
Page 67
... LOAD DATA AA ADDRESS 555 LOAD DATA 55 ADDRESS AAA LOAD DATA 60 SECTOR ADDRESS PAUSE 200 μs 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex) Address Format: A11 - A0 (Hex and A11 - A19 (Don’t Care). 2. Sector Lockdown feature enabled. AT91FR40162SB ( (2) 67 ...
Page 68
... AT91FR40162SB 68 Data Comments 0051h “Q” 0052h “R” 0059h “Y” 0002h 0000h 0041h 0000h 0000h 0000h 0000h 0000h 0027h V ...
Page 69
... Bit 1 – 8-word page, 0 – no, 1 – yes Undefined bits are “0” 0080h Location of protection register lock byte, the section’s first byte 0003h # of bytes in the factory prog section of prot register – 2*n 0003h # of bytes in the user prog section of prot register – 2*n AT91FR40162SB 69 ...
Page 70
... Idle Mode. 13.1 Peripheral Clocks The clock of each peripheral integrated in the AT91FR40162SB can be individually enabled and disabled by writing to the Peripheral Clock Enable (PS_PCER) and Peripheral Clock Disable Registers (PS_PCDR). The status of the peripheral clocks can be read in the Peripheral Clock Status Register (PS_PCSR) ...
Page 71
... Table 13-1. PS Memory Map Offset Register 0x00 Control Register 0x04 Peripheral Clock Enable Register 0x08 Peripheral Clock Disable Register 0x0C Peripheral Clock Status Register 6410B–ATARM–12-Jan-10 AT91FR40162SB Name Access PS_CR Write-only PS_PCER Write-only PS_PCDR Write-only PS_PCSR Read-only Reset State – ...
Page 72
... Offset: 0x00 31 30 – – – – – – – – • CPU: CPU Clock Disable effect Disables the CPU clock. The CPU clock is re-enabled by any enabled interrupt or by hardware reset. AT91FR40162SB – – – – – – – – – – ...
Page 73
... Enables the Timer Counter 2 clock. • PIO: Parallel IO Clock Enable effect Enables the Parallel IO clock. 6410B–ATARM–12-Jan- – – – – – – – – – TC1 TC0 US1 AT91FR40162SB – – – – – – – – PIO – – US0 73 ...
Page 74
... Disables the Timer Counter 0 clock. • TC1: Timer Counter 1 Clock Disable effect Disables the Timer Counter 1 clock. • TC2: Timer Counter 2 Clock Disable effect Disables the Timer Counter 2 clock. • PIO: Parallel IO Clock Disable effect Disables the Parallel IO clock. AT91FR40162SB – – – – ...
Page 75
... Timer Counter 2 clock is enabled. • PIO: Parallel IO Clock Status 0 = Parallel IO clock is disabled Parallel IO clock is enabled. 6410B–ATARM–12-Jan- – – – – – – – – – TC1 TC0 US1 AT91FR40162SB – – – – – – – – PIO – – US0 75 ...
Page 76
... AIC: Advanced Interrupt Controller The AT91FR40162SB has an 8-level priority, individually maskable, vectored interrupt control- ler. This feature substantially reduces the software and real-time overhead in handling internal and external interrupts. The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (standard interrupt request) inputs of the ARM7TDMI processor. The processor’ ...
Page 77
... Reserved – Reserved – Reserved IRQ0 External interrupt 0 IRQ1 External interrupt 1 IRQ2 External interrupt 2 – Reserved – Reserved – Reserved – Reserved – Reserved – Reserved – Reserved – Reserved – Reserved – Reserved – Reserved – Reserved – Reserved AT91FR40162SB 77 ...
Page 78
... This permits the AIC to assert the NIRQ line again when a higher priority unmasked interrupt occurs. At the end of the interrupt service routine, the end of interrupt command register (AIC_EOICR) must be written. This allows pending interrupts to be serviced. AT91FR40162SB 78 PC,[PC,# - &F20] Table 14-1 on page 77). 6410B– ...
Page 79
... With any sources programmed to be level sensitive, if the interrupt signal of the AIC input is de-asserted at the same time taken into account by the ARM7TDMI. • interrupt is asserted at the same time as the software is disabling the corresponding source through AIC_IDCR (this can happen due to the pipelining of the ARM core). 6410B–ATARM–12-Jan-10 PC,[PC,# -&F20] AT91FR40162SB 79 ...
Page 80
... The debug system must not write to the AIC_IVR as this would cause undesirable effects. The following table shows the main steps of an interrupt and the order in which they are per- formed according to the mode: AT91FR40162SB 80 113). 6410B–ATARM–12-Jan-10 ...
Page 81
... During this phase, an interrupt of priority higher than the current level will restart the sequence from step 1. Note that if the interrupt is 6410B–ATARM–12-Jan-10 level is the priority level of the current interrupt. must be read in order to de-assert NIRQ) AT91FR40162SB Normal Mode Protect Mode Read AIC_IVR Read AIC_IVR ...
Page 82
... NFIQ line. 6. Finally, the Link Register (r14_fiq) is restored into the PC after decrementing (with instruction sub pc, lr, #4 for example). This has effect of returning from the inter- AT91FR40162SB 82 The I bit in the SPSR is significant set, it indicates that the ARM core was just about to mask IRQ interrupts when the mask instruction was interrupted ...
Page 83
... SPSR. The F bit in the SPSR is significant set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ is masked). 6410B–ATARM–12-Jan-10 AT91FR40162SB 83 ...
Page 84
... Interrupt Set Command Register 0x130 End of Interrupt Command Register 0x134 Spurious Vector Register Note: 1. The reset value of this register depends on the level of the External IRQ lines. All other sources are cleared at reset. AT91FR40162SB 84 Name AIC_SMR0 AIC_SMR1 – AIC_SMR31 AIC_SVR0 AIC_SVR1 – ...
Page 85
... Level Sensitive x 1 Edge Triggered 6410B–ATARM–12-Jan- – – – – – – – – – – – AT91FR40162SB 26 25 – – – – – – PRIOR Code Label AIC_SRCTYPE AIC_SRCTYPE_EXT_LOW_LEVEL AIC_SRCTYPE_EXT_NEGATIVE_EDGE AIC_SRCTYPE_EXT_HIGH_LEVEL AIC_SRCTYPE_EXT_POSITIVE_EDGE Code Label AIC_SRCTYPE AIC_SRCTYPE_INT_LEVEL AIC_SRCTYPE_INT_EDGE 24 – ...
Page 86
... The IRQ Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register (1 to 31) is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the IRQ Vector Register reads 0. AT91FR40162SB ...
Page 87
... IRQID: Current IRQ Identifier (Code Label AIC_IRQID) The Interrupt Status Register returns the current interrupt source number. 6410B–ATARM–12-Jan- FIQV FIQV FIQV FIQV – – – – – – – – – – AT91FR40162SB – – – – – – – – – IRQID 87 ...
Page 88
... AIC Interrupt Mask Register Register Name: AIC_IMR Access Type:Read-only Reset Value: 0 Offset: 0x110 31 30 – – – – – – WDIRQ TC2IRQ • Interrupt Mask 0 = Corresponding interrupt is disabled Corresponding interrupt is enabled. AT91FR40162SB – – – – – – – – – TC1IRQ TC0IRQ ...
Page 89
... TC1IRQ TC0IRQ US1IRQ AT91FR40162SB – – – – – – – – – – NIRQ NFIQ – – – IRQ2 IRQ1 IRQ0 – ...
Page 90
... AIC Interrupt Clear Command Register Register Name: AIC_ICCR Access Type: Write-only Offset: 0x128 31 30 – – – – – – WDIRQ TC2IRQ • Interrupt Clear effect Clears corresponding interrupt. AT91FR40162SB – – – – – – – – – TC1IRQ ...
Page 91
... TC1IRQ TC0IRQ US1IRQ – – – – – – – – – – – – AT91FR40162SB – – – IRQ2 IRQ1 IRQ0 – – PIOIRQ US0IRQ SWIRQ FIQ – – – – – – – ...
Page 92
... AIC Spurious Vector Register Register Name:AIC_SPU Access Type:Read/Write Reset Value: 0 Offset: 0x134 • SPUVEC: Spurious Interrupt Vector Handler Address The user may store the address of the spurious interrupt handler in this register. AT91FR40162SB SPUVEC SPUVEC SPUVEC SPUVEC 6410B–ATARM–12-Jan-10 ...
Page 93
... PIO: Parallel I/O Controller The AT91FR40162SB has 32 programmable I/O lines. Six pins are dedicated as general pur- pose I/O pins (P16, P17, P18, P19, P23 and P24). Other I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins (see page 96) ...
Page 94
... User Interface Each individual I/O is associated with a bit position in the Parallel I/O user interface registers. Each of these registers are 32 bits wide parallel I/O line is not defined, writing to the corre- sponding bits has no effect. Undefined bits read zero. AT91FR40162SB 94 6410B–ATARM–12-Jan-10 ...
Page 95
... Figure 15-1. Parallel I/O Multiplexed with a Bi-directional Signal Pad Output Enable Pad Output Pad Pad Input 6410B–ATARM–12-Jan-10 PIO_OSR 1 0 PIO_PSR PIO_PSR PIO_PDSR Event Detection PIO_ISR PIO_IMR AT91FR40162SB Peripheral Output Enable PIO_ODSR Peripheral Output Peripheral Input PIOIRQ 95 ...
Page 96
... P29 A21/CS6 30 P30 A22/CS5 31 P31 A23/CS4 Note: 1. Bit Number refers to the data bit that corresponds to this signal in each of the User Interface registers. AT91FR40162SB 96 Peripheral Signal Description Timer 0 Clock signal Timer 0 Signal A Timer 0 Signal B Timer 1 Clock signal Timer 1 Signal A Timer 1 Signal B Timer 2 Clock signal ...
Page 97
... PIO_PDR PIO_PSR – PIO_OER PIO_ODR PIO_OSR – PIO_IFER PIO_IFDR PIO_IFSR – PIO_SODR PIO_CODR PIO_ODSR (1) PIO_PDSR PIO_IER PIO_IDR PIO_IMR (2) PIO_ISR AT91FR40162SB Access Reset State Write-only – Write-only – 0x01FFFFFF Read-only (see Table 15-1) – – Write-only – Write-only – Read-only 0 – – ...
Page 98
... P15 P14 This register is used to disable PIO control of individual pins. When the PIO control is disabled, the normal peripheral func- tion is enabled on the corresponding pin Disables PIO control (enables peripheral control) on the corresponding pin effect. AT91FR40162SB P29 P28 P27 P21 P20 ...
Page 99
... Enables the PIO output on the corresponding pin effect. 6410B–ATARM–12-Jan- P29 P28 P27 P21 P20 P19 P13 P12 P11 P29 P28 P27 P21 P20 P19 P13 P12 P11 AT91FR40162SB P26 P25 P24 P18 P17 P16 P10 P26 P25 P24 P18 P17 P16 P10 ...
Page 100
... This register shows the PIO pin control (output enable) status which is programmed in PIO_OER and PIO ODR. The defined value is effective only if the pin is controlled by the PIO. The register reads as follows The corresponding PIO is output on this line The corresponding PIO is input on this line. AT91FR40162SB 100 29 28 ...
Page 101
... Disables the glitch filter on the corresponding pin effect. 6410B–ATARM–12-Jan- P29 P28 P27 P21 P20 P19 P13 P12 P11 P29 P28 P27 P21 P20 P19 P13 P12 P11 AT91FR40162SB P26 P25 P24 P18 P17 P16 P10 P26 P25 P24 P18 P17 P16 P10 101 ...
Page 102
... P14 This register is used to set PIO output data. It affects the pin only if the corresponding PIO output line is enabled and if the pin is controlled by the PIO. Otherwise, the information is stored PIO output data on the corresponding pin is set effect. AT91FR40162SB 102 P29 P28 P27 21 ...
Page 103
... The output data for the corresponding line is programmed to 0. 6410B–ATARM–12-Jan- P29 P28 P27 P21 P20 P19 P13 P12 P11 P29 P28 P27 P21 P20 P19 P13 P12 P11 AT91FR40162SB P26 P25 P24 P18 P17 P16 P10 P26 P25 P24 P18 P17 P16 P10 103 ...
Page 104
... P23 P22 15 14 P15 P14 This register is used to enable PIO interrupts on the corresponding pin. It has effect whether PIO is enabled or not Enables an interrupt when a change of logic level is detected on the corresponding pin effect. AT91FR40162SB 104 P29 P28 P27 P21 P20 P19 13 12 ...
Page 105
... Interrupt is not enabled on the corresponding input pin. 6410B–ATARM–12-Jan- P29 P28 P27 P21 P20 P19 P13 P12 P11 P29 P28 P27 P21 P20 P19 P13 P12 P11 AT91FR40162SB P26 P25 P24 P18 P17 P16 P10 P26 P25 P24 P18 P17 P16 P10 105 ...
Page 106
... PIO is selected for the pin or not and whether the pin is an input or output. The register is reset to zero following a read, and at reset least one change has been detected on the corresponding pin since the register was last read change has been detected on the corresponding pin since the register was last read. AT91FR40162SB 106 29 28 ...
Page 107
... WD: Watchdog Timer The AT91FR40162SB has an internal watchdog timer which can be used to prevent system lock-up if the software becomes trapped in a deadlock. In normal operation the user reloads the watchdog at regular intervals before the timer overflow occurs overflow does occur, the watchdog timer generates one or a combination of the following signals, depending on the parameters in WD_OMR (Overflow Mode Register): • ...
Page 108
... Write 0x2340 to WD_OMR This step is unnecessary if the WD is already disabled (reset state). 2. Initialize the WD Clock Mode Register: Write 0x373C to WD_CMR (HPCV = 15 and WDCLKS = MCK/8) 3. Restart the timer: Write 0xC071 to WD_CR 4. Enable the watchdog: Write 0x2345 to WD_OMR (interrupt enabled) AT91FR40162SB 108 6410B–ATARM–12-Jan-10 ...
Page 109
... WD Base Address: 0xFFFF8000 (Code Label WD_BASE) Table 16-1. WD Memory Map Offset Register 0x00 Overflow Mode Register 0x04 Clock Mode Register 0x08 Control Register 0x0C Status Register 6410B–ATARM–12-Jan-10 AT91FR40162SB Name Access WD_OMR Read/Write WD_CMR Read/Write WD_CR Write-only WD_SR Read-only Reset State 0 0 – ...
Page 110
... Generation of a pulse on the pin NWDOVF by the Watch Dog is disabled When an overflow occurs, a pulse on the pin NWDOVF is generated. • OKEY: Overflow Access Key (Code Label WD_OKEY) Used only when writing WD_OMR. OKEY is read as 0. 0x234 = Write access in WD_OMR is allowed. Other value = Write access in WD_OMR is prohibited. AT91FR40162SB 110 – ...
Page 111
... Used only when writing WD_CMR. CKEY is read as 0. 0x06E: Write access in WD_CMR is allowed. Other value: Write access in WD_CMR is prohibited. 6410B–ATARM–12-Jan- – – – – – – CKEY HPCV AT91FR40162SB – – – – – – WDCLKS Code Label WD_WDCLKS WD_WDCLKS_MCK8 WD_WDCLKS_MCK32 ...
Page 112
... WDOVF: Watchdog Overflow (Code Label WD_WDOVF watchdog overflow watchdog overflow has occurred since the last restart of the watchdog counter or since internal or external reset. AT91FR40162SB 112 – – – – – – RSTKEY ...
Page 113
... SF: Special Function Registers The AT91FR40162SB provides registers to implement the following special functions. • Chip identification • RESET status • Protect Mode (see 17.1 Chip Identification Table 17-1 provides the Chip ID values for the products as listed. Table 17-1. Chip ID Values Product ...
Page 114
... Table 17-2. SF Memory Map Offset Register 0x00 Chip ID Register 0x04 Chip ID Extension Register 0x08 Reset Status Register 0x10 Reserved 0x14 Reserved 0x18 Protect Mode Register AT91FR40162SB 114 Name Access SF_CIDR Read-only SF_EXID Read-only SF_RSR Read-only – – – – SF_PMR Read/Write ...
Page 115
... NVPTYP Size 0 None 1 32K bytes 1 64K bytes 1 128K bytes 0 256K bytes Reserved Size 0 None Reserved AT91FR40162SB 26 25 ARCH 18 17 VDSIZ 10 9 NVPSIZ VERSION Code Label SF_NVPSIZ SF_NVPSIZ_NONE SF_NVPSIZ_32K SF_NVPSIZ_64K SF_NVPSIZ_128K SF_NVPSIZ_256K Code Label SF_NVDSIZ SF_NVDSIZ_NONE – – 115 ...
Page 116
... NVPTYP: Non Volatile Program Memory Type NVPTYP • EXT: Extension Flag (Code Label SF_EXT Chip ID has a single register definition without extensions extended Chip ID exists (to be defined in the future). AT91FR40162SB 116 Size 0 None 1 1K bytes 0 2K bytes 0 4K bytes 0 8K bytes Reserved AT91x40yyy Type Reserved “ ...
Page 117
... This field indicates whether the reset was demanded by the external system (via NRST the Watchdog internal reset request. Reset Cause of Reset 0x6C External Pin 0x53 Internal Watchdog 6410B–ATARM–12-Jan- – – – – – – – – – RESET AT91FR40162SB – – – – – – – – – Code Label SF_RESET SF_EXT_RESET SF_WD_RESET 117 ...
Page 118
... Write access in SF_PMR is allowed. Other value: Write access in SF_PMR is prohibited. • AIC: AIC Protect Mode Enable (Code Label SF_AIC The Advanced Interrupt Controller runs in Normal Mode The Advanced Interrupt Controller runs in Protect Mode. See Section 14.10 “Protect Mode” on page AT91FR40162SB 118 PMRKEY 21 ...
Page 119
... USART: Universal Synchronous Asynchronous Receiver Transmitter The AT91FR40162SB provides two identical, full-duplex, universal synchronous/asynchronous receiver/transmitters that interface to the APB and are connected to the Peripheral Data Controller. The main features are: • Programmable Baud Rate Generator • Parity, Framing and Overrun Error Detection • ...
Page 120
... After a hardware reset, the USART pins are not enabled by default (see must configure the PIO Controller before enabling the transmitter or receiver the user selects one of the internal clocks, SCK can be configured as a PIO. AT91FR40162SB 120 “PIO: Parallel I/O Controller” on page 93). The user 6410B– ...
Page 121
... In all cases external clock is used, the duration of each of its levels must be longer than the system clock (MCK) period. The external clock frequency must be at least 2.5 times lower than the system clock. Selected Clock = Selected Clock = CLK 16-bit Counter OUT > SYNC USCLKS [1] AT91FR40162SB SYNC 0 Divide Baud Rate Clock 121 ...
Page 122
... When configured for synchronous operation (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate clock low level is detected considered as a start. Data bits, parity bit and stop bit are sampled and the receiver waits for the next start bit. See example in AT91FR40162SB 122 RXD True Start Detection 0 ...
Page 123
... TIMEOUT bit in US_CSR is set. The user can restart the wait for a first character with the STTTO (Start Time-out) bit in US_CR. Calculation of time-out duration: 6410B–ATARM–12-Jan-10 SCK RXD True Start Detection = Value x Duration AT91FR40162SB Parity Bit x 4 Bit period Stop Bit 123 ...
Page 124
... US_CR. In this case, the next byte written to US_THR will be transmitted as an address. After this any byte transmitted will have the parity bit cleared. Figure 18-6. Synchronous and Asynchronous Modes: Character Transmission Example: 8-bit, parity enabled 1 stop Baud Rate AT91FR40162SB 124 Idle state duration between two characters Clock ...
Page 125
... Send the STTBRK command (write 0x0200 to US_CR) 3. Wait for the transmitter ready (TXRDY = 1 in US_CSR) 4. Send the STPBRK command (write 0x0400 to US_CR) The next byte can then be sent: 5. Wait for the transmitter ready (TXRDY = 1 in US_CSR) 6410B–ATARM–12-Jan-10 AT91FR40162SB 125 ...
Page 126
... Asynchronous Mode or at least one sample in Synchronous Mode. RXBRK is also asserted when an end of break is detected. Both the beginning and the end of a break can be detected by interrupt if the bit US_IMR.RXBRK is set. AT91FR40162SB 126 6410B–ATARM–12-Jan-10 ...
Page 127
... Advanced Interrupt Controller. US_IMR (Interrupt Mask Register) indicates the status of the corresponding bits. When a bit is set in US_CSR and the same bit is set in US_IMR, the interrupt line is asserted. 6410B–ATARM–12-Jan-10 The PDC is disabled if 9-bit character length is selected (MODE9 = 1) in US_MR. AT91FR40162SB 127 ...
Page 128
... RXD pin level has no effect and the TXD pin is held high idle state. Remote Loopback Mode directly connects the RXD pin to the TXD pin. The Transmitter and the Receiver are disabled and have no effect. This mode allows bit by bit re-transmission. Figure 18-7. Channel Modes AT91FR40162SB 128 Automatic Echo Receiver ...
Page 129
... Receiver Time-out Register 0x28 Transmitter Time-guard Register 0x2C Reserved 0x30 Receive Pointer Register 0x34 Receive Counter Register 0x38 Transmit Pointer Register 0x3C Transmit Counter Register 6410B–ATARM–12-Jan-10 AT91FR40162SB Name Access US_CR Write-only US_MR Read/Write US_IER Write-only US_IDR Write-only US_IMR Read-only US_CSR ...
Page 130
... Resets the status bits PARE, FRAME, OVRE and RXBRK in the US_CSR. • STTBRK: Start Break (Code Label US_STTBRK effect break is not being transmitted, start transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. AT91FR40162SB 130 – ...
Page 131
... STTTO: Start Time-out (Code Label US_STTTO effect Start waiting for a character before clocking the time-out counter. • SENDA: Send Address (Code Label US_SENDA effect Multi-drop Mode only, the next character written to the US_THR is sent with the address bit set. 6410B–ATARM–12-Jan-10 AT91FR40162SB 131 ...
Page 132
... X • CHRL: Character Length CHRL Start, stop and parity bits are added to the character length. • SYNC: Synchronous Mode Select (Code Label US_SYNC USART operates in Asynchronous Mode USART operates in Synchronous Mode. AT91FR40162SB 132 – – – – – – NBSTOP ...
Page 133
... CKLO: Clock Output Select (Code Label US_CLKO The USART does not drive the SCK pin The USART drives the SCK pin if USCLKS[ 6410B–ATARM–12-Jan-10 Synchronous (SYNC = 1) 1 stop bit Reserved 2 stop bits Reserved AT91FR40162SB Code Label US_PAR US_PAR_EVEN US_PAR_ODD US_PAR_SPACE US_PAR_MARK US_PAR_NO US_PAR_MULTIDROP ...
Page 134
... OVRE: Enable Overrun Error Interrupt (Code Label US_OVRE effect Enables Overrun Error Interrupt. • FRAME: Enable Framing Error Interrupt (Code Label US_FRAME effect Enables Framing Error Interrupt. • PARE: Enable Parity Error Interrupt (Code Label US_PARE effect Enables Parity Error Interrupt. AT91FR40162SB 134 – – – 21 ...
Page 135
... TIMEOUT: Enable Time-out Interrupt (Code Label US_TIMEOUT effect Enables Reception Time-out Interrupt. • TXEMPTY: Enable TXEMPTY Interrupt (Code Label US_TXEMPTY effect Enables TXEMPTY Interrupt. 6410B–ATARM–12-Jan-10 AT91FR40162SB 135 ...
Page 136
... OVRE: Disable Overrun Error Interrupt (Code Label US_OVRE effect Disables Overrun Error Interrupt. • FRAME: Disable Framing Error Interrupt (Code Label US_FRAME effect Disables Framing Error Interrupt. • PARE: Disable Parity Error Interrupt (Code Label US_PARE effect Disables Parity Error Interrupt. AT91FR40162SB 136 – – – 21 ...
Page 137
... TIMEOUT: Disable Time-out Interrupt (Code Label US_TIMEOUT effect Disables Receiver Time-out Interrupt. • TXEMPTY: Disable TXEMPTY Interrupt (Code Label US_TXEMPTY effect Disables TXEMPTY Interrupt. 6410B–ATARM–12-Jan-10 AT91FR40162SB 137 ...
Page 138
... Overrun Error Interrupt is Enabled • FRAME: Mask Framing Error Interrupt (Code Label US_FRAME Framing Error Interrupt is Disabled 1 = Framing Error Interrupt is Enabled • PARE: Mask Parity Error Interrupt (Code Label US_PARE Parity Error Interrupt is Disabled 1 = Parity Error Interrupt is Enabled AT91FR40162SB 138 – – ...
Page 139
... TIMEOUT: Mask Time-out Interrupt (Code Label US_TIMEOUT Receive Time-out Interrupt is Disabled 1 = Receive Time-out Interrupt is Enabled • TXEMPTY: Mask TXEMPTY Interrupt (Code Label US_TXEMPTY TXEMPTY Interrupt is Disabled TXEMPTY Interrupt is Enabled. 6410B–ATARM–12-Jan-10 AT91FR40162SB 139 ...
Page 140
... At least one byte has been transferred from the Receive Shift Register to the US_RHR when RxRDY was asserted since the last “Reset Status Bits” command. • FRAME: Framing Error (Code Label US_FRAME stop bit has been detected low since the last “Reset Status Bits” command. AT91FR40162SB 140 – ...
Page 141
... There are characters in either US_THR or the Transmit Shift Register or a Break is being transmitted There are no characters in US_THR and the Transmit Shift Register and Break is not active. Equal to zero when the USART is disabled or at reset. Transmitter Enable command (in US_CR) sets this bit to one. 6410B–ATARM–12-Jan-10 AT91FR40162SB 141 ...
Page 142
... TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. When number of data bits is less than 8 bits, the bits are right-aligned. AT91FR40162SB 142 – – – – – – 13 ...
Page 143
... Clock divisor bypass ( must not be used when internal clock MCK is selected (USCLKS = 0 Synchronous Mode, the value programmed must be even to ensure a 50:50 mark:space ratio. 6410B–ATARM–12-Jan- – – – – – – (1) AT91FR40162SB 26 25 – – – – (2) 24 – 16 – 143 ...
Page 144
... When a value is written to this register, a Start Time-out Command is automatically performed Disables the RX Time-out function. The Time-out counter is loaded with TO when the Start Time-out Command is given or when each new data character 255 received (after reception has started). Time-out duration = Bit period AT91FR40162SB 144 – – – ...
Page 145
... RXPTR: Receive Pointer RXPTR must be loaded with the address of the receive buffer. 6410B–ATARM–12-Jan- – – – – – – – – – RXPTR RXPTR RXPTR RXPTR AT91FR40162SB – – – – – – – – – 145 ...
Page 146
... Start Peripheral Data transfer if RXRDY is active. 18.10.14 USART Transmit Pointer Register Name: US_TPR Access Type:Read/Write Reset Value: 0 Offset: 0x38 • TXPTR: Transmit Pointer TXPTR must be loaded with the address of the transmit buffer. AT91FR40162SB 146 – – – 21 4920 19 – – – RXCTR ...
Page 147
... TXCTR must be loaded with the size of the transmit buffer. 0: Stop Peripheral Data Transfer dedicated to the transmitter 65535: Start Peripheral Data transfer if TXRDY is active. 6410B–ATARM–12-Jan- – – – – – – TXCTR TXCTR AT91FR40162SB – – – – – – 147 ...
Page 148
... TC: Timer Counter The AT91FR40162SB features a Timer Counter block which includes three identical 16-bit timer counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse gen- eration, delay timing and pulse width modulation. ...
Page 149
... XC0 Timer Counter TIOA Channel 1 XC1 TIOB XC2 SYNC TC1XC1S XC0 Timer Counter TIOA Channel 2 XC1 TIOB XC2 SYNC INT TC2XC2S AT91FR40162SB Parallel IO Controller TIOA0 TIOB0 INT TIOA1 TIOB1 INT TIOA2 TIOB2 Advanced Interrupt Controller TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 ...
Page 150
... Register) is set. The current value of the counter is accessible in real-time by reading TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. AT91FR40162SB 150 Description External Clock Inputs Capture Mode: General Purpose Input ...
Page 151
... In all cases external clock is used, the duration of each of its levels must be longer than the system clock (MCK) period. The external clock frequency must be at least 2.5 times lower than the system clock (MCK). CLKS MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024 XC0 XC1 XC2 BURST 1 AT91FR40162SB CLKI Selected Clock 151 ...
Page 152
... TIOB is an output not selected to be the external trigger. 19.3.5 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: AT91FR40162SB 152 Selected Trigger Clock CLKSTA ...
Page 153
... Whatever the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value may not read zero just after a trigger, espe- cially when a low frequency signal is selected as the clock. 6410B–ATARM–12-Jan-10 AT91FR40162SB 153 ...
Page 154
... ETRGS: External Trigger Status An external trigger on TIOA or TIOB has been detected since the last read of the status Note: AT91FR40162SB 154 All the status bits are set when the corresponding event occurs and they are automatically cleared when the Status Register is read. ...
Page 155
... RB is loaded TIOA Timer Counter Channel 6410B–ATARM–12-Jan-10 CLKI 16-bit Counter SWTRG CLK OVF RESET Trig CPCTRG ETRGEDG Edge Detector LDRA Edge Detector loaded AT91FR40162SB CLKSTA CLKEN CLKDIS LDBSTOP LDBDIS Register C Capture Capture Register A Register B Compare RC = LDRB Edge Detector INT 155 ...
Page 156
... The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be pro- grammed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR. AT91FR40162SB 156 6410B–ATARM–12-Jan-10 ...
Page 157
... TIOA Event Software Trigger External Event RC Compare RA Compare TIOB Event Software Trigger External Event RC Compare RB Compare All the status bits are set when the corresponding event occurs and they are automatically cleared when the Status Register is read. AT91FR40162SB 157 ...
Page 158
... Figure 19-5. Waveform Mode TCCLKS MCK/2 CLKI MCK/8 MCK/32 MCK/128 MCK/1024 XC0 XC1 XC2 BURST 1 SWTRG SYNC EEVT EEVTEDG Edge Detector TIOB Timer Counter Channel AT91FR40162SB 158 CLKSTA CLKEN Register A Register B Compare RA = Compare RB = 16-bit Counter CLK OVF RESET Trig CPCTRG ENETRG ...
Page 159
... Register C 0x20 Status Register 0x24 Interrupt Enable Register 0x28 Interrupt Disable Register 0x2C Interrupt Mask Register Note: 1. Read-only if WAVE = 0 6410B–ATARM–12-Jan-10 AT91FR40162SB Name Access See Table 19-3 See Table 19-3 See Table 19-3 TC_BCR Write-only TC_BMR Read/Write Name Access TC_CCR ...
Page 160
... Access Type:Write-only Offset: 0xC0 31 30 – – – – – – – – • SYNC: Synchro Command effect Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. AT91FR40162SB 160 – – – – – – – – – – ...
Page 161
... TC2XC2S Signal Connected to XC0 TCLK0 None TIOA1 TIOA2 Signal Connected to XC1 TCLK1 None TIOA0 TIOA2 Signal Connected to XC2 TCLK2 None TIOA0 TIOA1 AT91FR40162SB 26 25 – – – – – – TC1XC1S TC0XC0S 24 – 16 – 8 – 0 161 ...
Page 162
... Enables the clock if CLKDIS is not 1. • CLKDIS: Counter Clock Disable Command (Code Label TC_CLKDIS effect Disables the clock. • SWTRG: Software Trigger Command (Code Label TC_SWTRG effect software trigger is performed: the counter is reset and clock is started. AT91FR40162SB 162 – – – ...
Page 163
... XC2 is ANDed with the selected clock 6410B–ATARM–12-Jan- – – – – – – – – BURST CLKI AT91FR40162SB 26 25 – – LDRB LDRA 10 9 ABETRG ETRGEDG 2 1 TCCLKS Code Label TC_CLKS TC_CLKS_MCK2 TC_CLKS_MCK8 TC_CLKS_MCK32 TC_CLKS_MCK128 TC_CLKS_MCK1024 TC_CLKS_XC0 TC_CLKS_XC1 TC_CLKS_XC2 ...
Page 164
... Capture Mode is disabled (Waveform Mode is enabled). • LDRA: RA Loading Selection LDRA Edge 0 0 None 0 1 Rising edge of TIOA 1 0 Falling edge of TIOA 1 1 Each edge of TIOA AT91FR40162SB 164 Code Label TC_ETRGEDG TC_ETRGEDG_EDGE_NONE TC_ETRGEDG_RISING_EDGE TC_ETRGEDG_FALLING_EDGE TC_ETRGEDG_BOTH_EDGE Code Label TC_ABETRG TC_ABETRG_TIOB TC_ABETRG_TIOA Code Label TC_LDRA TC_LDRA_EDGE_NONE TC_LDRA_RISING_EDGE TC_LDRA_FALLING_EDGE TC_LDRA_BOTH_EDGE 6410B– ...
Page 165
... LDRB: RB Loading Selection LDRB Edge 0 0 None 0 1 Rising edge of TIOA 1 0 Falling edge of TIOA 1 1 Each edge of TIOA 6410B–ATARM–12-Jan-10 AT91FR40162SB Code Label TC_LDRB TC_LDRB_EDGE_NONE TC_LDRB_RISING_EDGE TC_LDRB_FALLING_EDGE TC_LDRB_BOTH_EDGE 165 ...
Page 166
... Counter is incremented on falling edge of the clock. • BURST: Burst Signal Selection BURST Selected BURST 0 0 The clock is not gated by an external signal XC0 is ANDed with the selected clock XC1 is ANDed with the selected clock XC2 is ANDed with the selected clock. AT91FR40162SB 166 BEEVT AEEVT – ENETRG 5 ...
Page 167
... RC Compare resets the counter and starts the counter clock. • WAVE = 1 (Code Label TC_WAVE Waveform Mode is disabled (Capture Mode is enabled Waveform Mode is enabled. 6410B–ATARM–12-Jan-10 External Event TIOB Direction (1) Input Output Output Output AT91FR40162SB Code Label TC_EEVTEDG TC_EEVTEDG_EDGE_NONE TC_EEVTEDG_RISING_EDGE TC_EEVTEDG_FALLING_EDGE TC_EEVTEDG_BOTH_EDGE Code Label TC_EEVT TC_EEVT_TIOB TC_EEVT_XC0 TC_EEVT_XC1 ...
Page 168
... Clear 1 1 Toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG Effect 0 0 None 0 1 Set 1 0 Clear 1 1 Toggle AT91FR40162SB 168 Code Label TC_ACPA TC_ACPA_OUTPUT_NONE TC_ACPA_SET_OUTPUT TC_ACPA_CLEAR_OUTPUT TC_ACPA_TOGGLE_OUTPUT Code Label TC_ACPC TC_ACPC_OUTPUT_NONE TC_ACPC_SET_OUTPUT TC_ACPC_CLEAR_OUTPUT TC_ACPC_TOGGLE_OUTPUT Code Label TC_AEEVT TC_AEEVT_OUTPUT_NONE TC_AEEVT_SET_OUTPUT TC_AEEVT_CLEAR_OUTPUT ...
Page 169
... Toggle • BSWTRG: Software Trigger Effect on TIOB BSWTRG Effect 0 0 None 0 1 Set 1 0 Clear 1 1 Toggle 6410B–ATARM–12-Jan-10 AT91FR40162SB Code Label TC_BCPB TC_BCPB_OUTPUT_NONE TC_BCPB_SET_OUTPUT TC_BCPB_CLEAR_OUTPUT TC_BCPB_TOGGLE_OUTPUT Code Label TC_BCPC TC_BCPC_OUTPUT_NONE TC_BCPC_SET_OUTPUT TC_BCPC_CLEAR_OUTPUT TC_BCPC_TOGGLE_OUTPUT Code Label TC_BEEVT TC_BEEVT_OUTPUT_NONE TC_BEEVT_SET_OUTPUT TC_BEEVT_CLEAR_OUTPUT ...
Page 170
... CV contains the counter value in real-time. 19.6.7 TC Register A Register Name:TC_RA Access Type:Read-only if WAVE = 0, Read/Write if WAVE = 1 Reset Value: 0 Offset: 0x14 31 30 – – – – • RA: Register A (Code Label TC_RA) RA contains the Register A value in real-time. AT91FR40162SB 170 – – – – – – ...
Page 171
... RC: Register C (Code Label TC_RC) RC contains the Register C value in real-time. 6410B–ATARM–12-Jan- – – – – – – – – – – – – AT91FR40162SB – – – – – – – – – – – – 171 ...
Page 172
... RB Load has not occurred since the last read of the Status Register or WAVE = Load has occurred since the last read of the Status Register, if WAVE = 0. • ETRGS: External Trigger Status (Code Label TC_ETRGS External trigger has not occurred since the last read of the Status Register. AT91FR40162SB 172 – ...
Page 173
... MTIOB: TIOB Mirror (Code Label TC_MTIOB TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high. 6410B–ATARM–12-Jan-10 AT91FR40162SB 173 ...
Page 174
... Enables the RC Compare Interrupt. • LDRAS: RA Loading (Code Label TC_LDRAS effect Enables the RA Load Interrupt. • LDRBS: RB Loading (Code Label TC_LDRBS effect Enables the RB Load Interrupt. • ETRGS: External Trigger (Code Label TC_ETRGS effect Enables the External Trigger Interrupt. AT91FR40162SB 174 – – – – ...
Page 175
... ETRGS: External Trigger (Code Label TC_ETRGS effect Disables the External Trigger Interrupt. 6410B–ATARM–12-Jan- – – – – – – – – – LDRAS CPCS CPBS AT91FR40162SB – – – – – – – – – CPAS LOVRS COVFS 175 ...
Page 176
... The Load RA Interrupt is disabled The Load RA Interrupt is enabled. • LDRBS: RB Loading (Code Label TC_LDRBS The Load RB Interrupt is disabled The Load RB Interrupt is enabled. • ETRGS: External Trigger (Code Label TC_ETRGS The External Trigger Interrupt is disabled The External Trigger Interrupt is enabled. AT91FR40162SB 176 – – – ...
Page 177
... AT91FR40162SB Electrical Characteristics 20.1 Absolute Maximum Ratings Table 20-1. Absolute Maximum Ratings* Operating Temperature (Industrial) . -40⋅ 85⋅ C Storage Temperature..................... -60⋅ 150⋅ C Voltage on Any Input Pin with Respect to Ground ................................................. -0.3V to max of V .......................................................... + 0.3V and 3.6V Maximum Operating Voltage (V DDIO Maximum Operating Voltage (V DDCORE 6410B– ...
Page 178
... AT91FR40162SB DC Characteristics The following characteristics are applicable to the Operating Temperature range: T specified and are certified for a Junction Temperature up to 100⋅ C. Table 20-2. DC Characteristics Symbol Parameter V DC Supply I/Os DDIO V DC Supply Core DDCORE V Input Low Voltage IL V Input High Voltage ...
Page 179
... Product Identification Software Notes can Manufacturer Code: 001FH, Device Code: 01C0H 6410B–ATARM–12-Jan-10 Condition Min I 0. MHz OUT mA 2 RESET ( AT91FR40162SB Typ Max 0 OUT High-Z High-Z X High-Z Manufacturer A19 = Code A19 = V Device Code IH IL Units µA µA µ (2) (2) 179 ...
Page 180
... Reset Normal Idle Note: Table 20-6. Peripheral PIO Controller Timer/Counter Channel Timer/Counter Block (3 Channels) USART AT91FR40162SB 180 = 1.8V 25⋅ the AT91EB40A Evaluation Board and are given DDCORE A Power Consumption on VDDCORE Conditions Fetch in ARM mode from internal SRAM All peripheral clocks activated ...
Page 181
... D 6410B–ATARM–12-Jan-10 Conditions Conditions MCKO C derating MCKO MCKO C derating MCKO t CH 2.0V 0. 0.5 V 0.5 V DDIO DDIO t CDHL AT91FR40162SB Min Max 82.1 12.2 5.0 5.5 Min Max 4.4 6.6 0.199 0.295 4.5 6.7 0.153 0.228 0.8V 0. Min Max 3(t /2) 7 Units ...
Page 182
... Figure 20-2. MCKO Relative to NRST NRST MCKO AT91FR40162SB 182 t D 6410B–ATARM–12-Jan-10 ...
Page 183
... I/O Power Supply given in is the capacitance load on the considered output pin. is the load derating factor depending on the capacitance load on the related output 1. The user must take into account the package capacitance load contribution (C Table 20-2 on page 178. AT91FR40162SB DDIO ⎛ ∑ δ × ...
Page 184
... Temperature Derating Factor Figure 21-1. Derating Curve for Different Operating Temperatures 21.1.3 Core Voltage Derating Factor Figure 21-2. Core Voltage Derating Factor AT91FR40162SB 184 1,2 1,1 1 0,9 0,8 -60 -40 - Operating Temperature ° 0,5 1 1,05 1,1 1,15 1,2 1,25 1,3 ...
Page 185
... IO Voltage Derating Factor Figure 21-3. 6410B–ATARM–12-Jan-10 Derating Factor for Different V DDIO 1,6 1,5 1,4 1,3 1,2 1,1 1 0,9 0,8 2 2,2 2,4 2,6 V DDIO AT91FR40162SB Power Supply Levels Derating Factor for Typ Case is 1 2,8 3 3,2 3,4 Voltage Level 3,6 185 ...
Page 186
... Waveform Total-count Detection mode. The inputs have to meet the minimum pulse width and minimum input period shown in Table 21-3. Symbol TC 1 Table 21-4. Symbol TC 2 AT91FR40162SB 186 21-2, and represented in Figure 21-4. USART Input Minimum Pulse Width Parameter SCK/RXD Minimum Pulse Width USART Minimum Input Period Parameter ...
Page 187
... Reset Minimum Pulse Width Parameter NRST Minimum Pulse Width RST and represented in Figure AIC Input Minimum Pulse Width Parameter FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Minimum Pulse Width AIC Input Minimum Period Parameter AIC Minimum Input Period AT91FR40162SB TC 2 3(t /2) CP Table 21-5 and as represented in Min Pulse-width 10 21-7 ...
Page 188
... ICE 2 ICE 3 ICE 4 ICE 5 ICE 6 ICE 7 ICE 8 ICE 9 AT91FR40162SB 188 MCKI AIC 1 PIO Input Minimum Pulse Width Parameter PIO Input Minimum Pulse Width PIO ICE Interface Timing Specifications Parameter Conditions NTRST Minimum Pulse Width NTRST High Recovery to TCK High NTRST High Removal from ...
Page 189
... Figure 21-9. ICE Interface Signal NTRST TMS/TDI 6410B–ATARM–12-Jan-10 ICE 0 TCK ICE 3 TDO ICE 8 ICE 9 AT91FR40162SB ICE ICE 2 1 ICE 5 ICE 4 ICE ICE 6 7 189 ...
Page 190
... MCKI Rising to NWR Inactive (Wait States) 10 EBI MCKI Rising D15 Out Valid 11 EBI NWR High to NUB Change 12 EBI NWR High to NLB/A0 Change 13 EBI NWR High A23 Change 14 EBI NWR High to Chip Select Inactive 15 AT91FR40162SB 190 Conditions NUB C derating NUB NLB C derating NLB ...
Page 191
... C derating NRD NRD (1) C derating NRD NRD (2) C derating NRD (5) ( NUB C derating NUB NLB C derating NLB ADD C derating ADD NCS C derating NCS AT91FR40162SB Min Max Units -0.080 ns/pF 0.044 ns/ -0.080 ns/pF 0.044 ns/pF 2 EBI 0 ns/ ns/pF Min Max Units 4 ...
Page 192
... If this condition is not met, the action depends on the read protocol intended for use. • Early Read Protocol: Programing an additional t • Standard Read Protocol: Programming an additional t 2. Applicable only for chip select programmed with 0 wait state. If this condition is not met, at least one wait state must be programmed. AT91FR40162SB 192 Conditions ...
Page 193
... EBI 23 EBI 33 EBI EBI 22 24 EBI 34 EBI 31 EBI 25 EBI EBI 9 7 EBI 19 EBI 8 EBI 11 EBI 16 1. Early Read Protocol. 2. Standard Read Protocol. AT91FR40162SB EBI 4 EBI 27-30 EBI 32 EBI 26 EBI 12-15 EBI 10 EBI 20 EBI EBI bis 17 18 EBI 18 No Wait Wait 193 ...
Page 194
... OE (3)( 21.4.1 AC Read Waveforms Figure 21-11. AC Read Waveforms RESET Notes: AT91FR40162SB 194 Parameter Read Cycle Time Address to Output Delay CE to Output Delay OE to Output Delay Output Float Output Hold from OE Address, whichever occurred first RESET to Output Delay (1) (2) (3) (4) ADDRESS ADDRESS VALID ...
Page 195
... Figure 21-12. Input Test Waveforms and Measurement Level 21.4.3 Output Test Load Figure 21-13. Output Test Load 21.4.4 Pin Capacitance Table 21-15. Pin Capacitance MHz 25°C Symbol OUT Note: 1. This parameter is characterized and is not 100% tested. 6410B–ATARM–12-Jan- < (1) Conditions OUT AT91FR40162SB Typ Max Units pF pF 195 ...
Page 196
... Address Hold Time AH t Chip Select Setup Time CS t Chip Select Hold Time CH t Write Pulse Width ( Write Pulse Width High WPH t Data Setup Time Data, OE Hold Time DH OEH 21.5.1 WE Controlled Figure 21-14. WE Controlled AT91FR40162SB 196 Min Max Units 6410B–ATARM–12-Jan-10 ...
Page 197
... CE Controlled Figure 21-15. CE Controlled 6410B–ATARM–12-Jan-10 AT91FR40162SB 197 ...
Page 198
... Sector Erase Cycle Time (32K Word Sectors) SEC2 t Erase Suspend Time ES t Program Suspend Time PS t Delay between Erase Resume and Erase Suspend ERES 21.6.1 Program Cycle Waveforms Figure 21-16. Program Cycle Waveforms A19 DATA AT91FR40162SB 198 PROGRAM CYCLE WPH 555 AAA 555 ...
Page 199
... OE must be high only when WE and CE are both low. 2. For chip erase, the address should be 555. For sector erase, the address depends on what sector erased. (See footnote page 63.) 3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H. AT91FR40162SB t WPH 555 555 AAA ...
Page 200
... OE t Write Recovery Time WR Notes: 1. These parameters are characterized and not 100% tested. 2. See t spec in “AC Flash Read Characteristics” on page OE 21.7.1 Data Polling Waveforms Figure 21-18. Data Polling Waveforms I/O7 A0-A19 AT91FR40162SB 200 (1) 194. t OEH HIGH Min Typ Max 10 10 ...