AT91FR40162SB-CU-999 Atmel, AT91FR40162SB-CU-999 Datasheet - Page 54

• Manufacturer Part Number: AT91FR40162SB-CU-999
• Description: IC MCU 32BIT RISC 121BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91FR40162SB-CU-999

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 75MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 2MB (1M x 16)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-BGA
• Data Bus Width: 32 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

12.2.7
12.2.8
12.2.9
54
AT91FR40162SB
DATA Polling
Toggle Bit
Erase/Program Status Bit
ues, “00” or “01”. If the configuration register is set to “00”, the part will automatically return to the
read mode after a successful program or erase operation. If the configuration register is set to a
“01”, a Product ID Exit command must be given after a successful program or erase operation
before the part will return to the read mode. It is important to note that whether the configuration
register is set to a “00” or to a “01”, any unsuccessful program or erase operation requires using
the Product ID Exit command to return the device to read mode. The default value (after power-
up) for the configuration register is “00”. Using the four-bus cycle Set Configuration Register
command as shown in
configuration register can be changed. Voltages applied to the RESET pin will not alter the value
of the configuration register. The value of the configuration register will affect the operation of
the I/O7 status bit as described below.
The Flash Memory features Data Polling to indicate the end of a program cycle. If the status
configuration register is set to a “00”, during a program cycle an attempted read of the last
byte/word loaded will result in the complement of the loaded data on I/O7. Once the program
cycle has been completed, true data is valid on all outputs and the next cycle may begin. During
a chip or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the
program or erase cycle has completed, true data will be read from the device. Data Polling may
begin at any time during the program cycle. Please see
If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the
device is actively programming or erasing data. I/O7 will go high when the device has completed
a program or erase operation. Once I/O7 has gone high, status information on the other pins can
be checked.
The Data Polling status bit must be used in conjunction with the erase/program status bit as
shown in the algorithm in
In addition to Data Polling the Flash Memory provides another method for determining the end of
a program or erase cycle. During a program or erase operation, successive attempts to read
data from the memory will result in I/O6 toggling between one and zero. Once the program cycle
has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may
begin at any time during a program cycle. Please see
details.
The toggle bit status bit should be used in conjunction with the erase/program status bit as
shown in the algorithm in
The device offers a status bit on I/O5, which indicates whether the program or erase operation
has exceeded a specified internal pulse count limit. If the status bit is a “1”, the device is unable
to verify that an erase or a byte/word program operation has been successfully performed. If a
program (Sector Erase) command is issued to a protected sector, the protected sector will not
be programmed (erased). The device will go to a status read mode and the I/O5 status bit will be
set high, indicating the program (erase) operation did not complete as requested. Once the
erase/program status bit has been set to a “1”, the system must write the Product ID Exit com-
mand to return to the read mode. The erase/program status bit is a “0” while the erase or
program operation is still in progress. Please see
Table 12-2, “Command Definition Table,” on page
Figure 12-2 on page 58
Figures 12-4 and
and
12-5
“Status Bit Table” on page 62
and
on
Figure 12-3 on page
Table 12-1 on page 62
“Status Bit Table” on page 62
page
60.
59.
63, the value of the
6410B–ATARM–12-Jan-10
for more details.
for more details.
for more