P89C662HFA/00,512 NXP Semiconductors, P89C662HFA/00,512 Datasheet - Page 13

• Manufacturer Part Number: P89C662HFA/00,512
• Description: IC 80C51 MCU FLASH 32K 44-PLCC
• Manufacturer: NXP Semiconductors
• Series: 89Cr

Specifications of P89C662HFA/00,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 568-1270-5; 935267446512; P89C662HFA

Philips Semiconductors
SIO1 Implementation and Operation
Figure 3 shows how the on-chip I
and the following text describes the individual blocks.
Input Filters and Output Stages
The input filters have I
is less than 1.5 V, the input logic level is interpreted as 0; if the input
voltage is greater than 3.0 V, the input logic level is interpreted as 1.
Input signals are synchronized with the internal clock (f
spikes shorter than three oscillator periods are filtered out.
The output stages consist of open drain transistors that can sink
3mA at V
clamping diodes to V
bus and V
Address Register, S1ADR
This 8-bit special function register may be loaded with the 7-bit slave
address (7 most significant bits) to which SIO1 will respond when
programmed as a slave transmitter or receiver. The LSB (GC) is
used to enable general call address (00H) recognition.
2002 Oct 28
SDA
SCL
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
CONDITION
START
OUT
S
DD
is switched off, the I
< 0.4 V. These open drain outputs do not have
I
2
C bus
MSB
1
DD
2
C compatible input levels. If the input voltage
. Thus, if the device is connected to the I
SLAVE ADDRESS
2
P1.7/SDA
2
2
C bus interface is implemented,
C bus is not affected.
P89C66x
P1.6/SCL
7
DIRECTION
Figure 1. Typical I
SIGNAL FROM RECEIVER
Figure 2. Data Transfer on the I
ACKNOWLEDGMENT
R/W
BIT
8
OSC
/4), and
OTHER DEVICE WITH
ACK
9
I
2
R
2
C
P
C INTERFACE
2
13
C Bus Configuration
R
Comparator
The comparator compares the received 7-bit slave address with its
own slave address (7 most significant bits in S1ADR). It also
compares the first received 8-bit byte with the general call address
(00H). If an equality is found, the appropriate status bits are set and
an interrupt is requested.
Shift Register, S1DAT
This 8-bit special function register contains a byte of serial data to
be transmitted or a byte which has just been received. Data in
S1DAT is always shifted from right to left; the first bit to be
transmitted is the MSB (bit 7) and, after a byte has been received,
the first bit of received data is located at the MSB of S1DAT. While
data is being shifted out, data on the bus is simultaneously being
shifted in; S1DAT always contains the last byte present on the bus.
Thus, in the event of lost arbitration, the transition from master
transmitter to slave receiver is made with the correct data in S1DAT.
P
V
1
CLOCK LINE HELD LOW WHILE
INTERRUPTS ARE SERVICED
DD
REPEATED IF MORE BYTES
2
ARE TRANSFERRED
C Bus
P89C660/P89C662/P89C664/
2
OTHER DEVICE WITH
SIGNAL FROM RECEIVER
I
2
3–8
C INTERFACE
ACKNOWLEDGMENT
ACK
9
SU01710
SDA
SCL
P89C668
P/S
Product data
CONDITION
CONDITION
REPEATED
SU00965
START
STOP