PXAG49KBBD/00,557 NXP Semiconductors, PXAG49KBBD/00,557 Datasheet - Page 31
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PXAG49KBBD/00,557
Manufacturer Part Number
PXAG49KBBD/00,557
Description
IC XA MCU 16BIT FLASH 64K 44LQFP
Manufacturer
NXP Semiconductors
Series
XAr
Datasheet
1.PXAG49KBA00512.pdf
(42 pages)
Specifications of PXAG49KBBD/00,557
Core Processor
XA
Core Size
16-Bit
Speed
30MHz
Connectivity
UART/USART
Peripherals
PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
44-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Other names
568-1302
935267442557
PXAG49KBBD
935267442557
PXAG49KBBD
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PXAG49KBBD/00,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
INTERRUPTS
The XA-G49 supports 38 vectored interrupt sources. These include
9 maskable event interrupts, 7 exception interrupts, 16 trap
interrupts, and 7 software interrupts. The maskable interrupts each
have 8 priority levels and may be globally and/or individually enabled
or disabled.
The XA defines four types of interrupts:
Exception interrupts, software interrupts, and trap interrupts are
generally standard for XA derivatives and are detailed in the XA
User Guide . Event interrupts tend to be different on different XA
derivatives.
Table 8. Interrupt Vectors
EXCEPTION/TRAPS PRECEDENCE
EVENT INTERRUPTS
SOFTWARE INTERRUPTS
2001 Jun 27
Exception Interrupts – These are system level errors and other
very important occurrences which include stack overflow,
divide-by-0, and reset.
Event interrupts – These are peripheral interrupts from devices
such as UARTs, timers, and external interrupt inputs.
Software Interrupts – These are equivalent of hardware
interrupt, but are requested only under software control.
Trap Interrupts – These are TRAP instructions, generally used to
call system services in a multi-tasking system.
XA 16-bit microcontroller family
64K Flash/2K RAM, watchdog, 2 UARTs
Reset (h/w, watchdog, s/w)
Breakpoint (h/w trap 1)
Trace (h/w trap 2)
Stack Overflow (h/w trap 3)
Divide by 0 (h/w trap 4)
User RETI (h/w trap 5)
TRAP 0– 15 (software)
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Timer 2 interrupt
Serial port 0 Rx
Serial port 0 Tx
Serial port 1 Rx
Serial port 1 Tx
Software interrupt 1
Software interrupt 2
Software interrupt 3
Software interrupt 4
Software interrupt 5
Software interrupt 6
Software interrupt 7
DESCRIPTION
DESCRIPTION
DESCRIPTION
TF2(EXF2)
FLAG BIT
FLAG BIT
SWR1
SWR2
SWR3
SWR4
SWR5
SWR6
SWR7
TF0
TF1
RI.0
RI.1
TI.0
TI.1
IE0
IE1
00AC–00AF
00A8–00AB
0088–008B
008C–008F
00A0–00A3
00A4–00A7
0080–0083
0084–0087
0090–0093
ADDRESS
010C–010F
0100–0103
0104–0107
0108–010B
ADDRESS
0110–0113
0114–0117
0118–011B
VECTOR
VECTOR
VECTOR ADDRESS
000C–000F
0000–0003
0004–0007
0008–000B
0010–0013
0014–0017
0040–007F
31
ENABLE BIT
ENABLE BIT
The XA-G49 supports a total of 9 maskable event interrupt sources
(for the various XA peripherals), seven software interrupts, 5
exception interrupts (plus reset), and 16 traps. The maskable event
interrupts share a global interrupt disable bit (the EA bit in the IEL
register) and each also has a separate individual interrupt enable bit
(in the IEL or IEH registers). Only three bits of the IPA register
values are used on the XA-G49. Each event interrupt can be set to
occur at one of 8 priority levels via bits in the Interrupt Priority (IP)
registers, IPA0 through IPA5. The value 0 in the IPA field gives the
interrupt priority 0, in effect disabling the interrupt. A value of 1 gives
the interrupt a priority of 9, the value 2 gives priority 10, etc. The
result is the same as if all four bits were used and the top bit set for
all values except 0. Details of the priority scheme may be found in
the XA User Guide.
The complete interrupt vector list for the XA-G49, including all 4
interrupt types, is shown in the following tables. The tables include
the address of the vector for each interrupt, the related priority
register bits (if any), and the arbitration ranking for that interrupt
source. The arbitration ranking determines the order in which
interrupts are processed if more than one interrupt of the same
priority occurs simultaneously.
SWE1
SWE2
SWE3
SWE4
SWE5
SWE6
SWE7
ERI0
ERI1
ETI0
ETI1
EX0
EX1
ET0
ET1
ET2
INTERRUPT PRIORITY
IPA4.2–0 (PRIO)
IPA5.2–0 (PRT1)
IPA4.6–4 (PTIO)
IPA5.6–4 (PTI1)
IPA0.2–0 (PX0)
IPA0.6–4 (PT0)
IPA1.2–0 (PX1)
IPA1.6–4 (PT1)
IPA2.2–0 (PT2)
INTERRUPT PRIORITY
ARBITRATION RANKING
(fixed at 1)
(fixed at 2)
(fixed at 3)
(fixed at 4)
(fixed at 5)
(fixed at 6)
(fixed at 7)
0 (High)
1
1
1
1
1
1
ARBITRATION
RANKING
XA-G49
Preliminary data
10
2
3
4
5
6
7
8
9