EP9301-CQ Cirrus Logic Inc, EP9301-CQ Datasheet - Page 157
EP9301-CQ
Manufacturer Part Number
EP9301-CQ
Description
IC ARM920T MCU 166MHZ 208-LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EDB9301.pdf
(5 pages)
2.EDB9301.pdf
(4 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9301-IQ.pdf
(41 pages)
Specifications of EP9301-CQ
Core Processor
ARM9
Core Size
16/32-Bit
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
598-1248
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUS
Quantity:
3 390
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUSLOGIC
Quantity:
20 000
Company:
Part Number:
EP9301-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EDB9301 PDF datasheet
- EDB9301 PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9301-IQ PDF datasheet #4
- Current page: 157 of 824
- Download datasheet (13Mb)
I2SClkDiv
DS785UM1
MENA
SENA
31
15
Address:
Default:
Definition:
Bit Descriptions:
SLAVE
ESEL
30
14
ORIDE
PSEL
29
13
28
12
0x8093_008C - Read/Write, Software locked
0x0000_0000
Configures the I
RSVD:
SENA:
SLAVE:
ORIDE:
DROP:
SPOL:
LRDIV:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
2
S block audio clocks MCLK, SCLK, and LRCLK.
25
9
Reserved. Unknown During Read.
Enable audio clock generation.
I
slave. SCLK and LRCLK are chip inputs. The clock
configuration controls in this register are ignored in slave
mode.
Override I
1 - Override the SAI_MSTR_CLK_CFG from the I
and use the I2SClkDiv Register settings.
0 - Use the I2S SAI_MSTR_CLK_CFG signals.
Drop SCLK clocks.
1 - When in 64x mode, drop 8 SCLKs.
0 - Do not drop SCLKs.
SCLK polarity. Defines the SCLK edge that aligns to
LRCLK transitions.
1 - LRCLK transitions on the falling SCLK edge.
0 - LRCLK transitions on the rising SCLK edge.
LRCLK divide select.
00 - LRCK = SCLK / 32
01 - LRCK = SCLK / 64
10 - LRCK = SCLK / 128
11 - Reserved
2
RSVD
PDIV
S slave. Configures the I
24
8
2
RSVD
S master configuration.
23
7
22
6
21
5
2
S clock system to operate as a
DROP
20
4
SPOL
MDIV
19
3
EP93xx User’s Guide
System Controller
18
2
LRDIV
17
1
2
S block
SDIV
16
5-31
0
5
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