EP9301-CQ Cirrus Logic Inc, EP9301-CQ Datasheet - Page 443
![IC ARM920T MCU 166MHZ 208-LQFP](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-CQ
Manufacturer Part Number
EP9301-CQ
Description
IC ARM920T MCU 166MHZ 208-LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EDB9301.pdf
(5 pages)
2.EDB9301.pdf
(4 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9301-IQ.pdf
(41 pages)
Specifications of EP9301-CQ
Core Processor
ARM9
Core Size
16/32-Bit
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
598-1248
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUS
Quantity:
3 390
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUSLOGIC
Quantity:
20 000
Company:
Part Number:
EP9301-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EDB9301 PDF datasheet
- EDB9301 PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9301-IQ PDF datasheet #4
- Current page: 443 of 824
- Download datasheet (13Mb)
DS785UM1
11.2.2 Host Controller Interface
11.2.2.1 Communication Channels
There are two communication channels between the Host Controller and the Host Controller
Driver. The first channel uses a set of operational registers located on the HC. The Host
Controller is the target for all communication on this channel. The operational registers
contain control, status, and list pointer registers. Within the operational register set is a
pointer to a location in shared memory named the Host Controller Communications Area
(HCCA). The HCCA is the second communication channel. The Host Controller is the master
for all communication on this channel. The HCCA contains the head pointers to the interrupt
Endpoint Descriptor lists, the head pointer to the done queue, and status information
associated with start-of-frame processing.
Device Enumeration
OpenHCL
Device Register
in memory space
Operational
Mode
HCCA
Status
Event
Frame Int
Ratio
Control
Bulk
Registers
Figure 11-2. Communication Channels
Copyright 2007 Cirrus Logic
Shared RAM
Host Controller
Communications Area
Interrupt 0
Interrupt 1
Interrupt 2
...
Interrupt 31
...
...
Done
Figure 11-2
shows the communication channels.
Universal Serial Bus Host Controller
EP93xx User’s Guide
11-3
11
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