EP9301-CQ Cirrus Logic Inc, EP9301-CQ Datasheet - Page 777
![IC ARM920T MCU 166MHZ 208-LQFP](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-CQ
Manufacturer Part Number
EP9301-CQ
Description
IC ARM920T MCU 166MHZ 208-LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EDB9301.pdf
(5 pages)
2.EDB9301.pdf
(4 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9301-IQ.pdf
(41 pages)
Specifications of EP9301-CQ
Core Processor
ARM9
Core Size
16/32-Bit
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
598-1248
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUS
Quantity:
3 390
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUSLOGIC
Quantity:
20 000
Company:
Part Number:
EP9301-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EDB9301 PDF datasheet
- EDB9301 PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9301-IQ PDF datasheet #4
- Current page: 777 of 824
- Download datasheet (13Mb)
DS785UM1
27.2.7 DMA Request Latency
27.2.7.1 DMA Request Deassertion
27.2.7.2 DMA Request Latency Overview
latching of the data. It is calculated that the cycle time of AHB clock has to be smaller than
(IDE cycle time)*2/3. For different UDMA speed modes, the minimum AHB clock speeds are
listed below. There is no special speed constraint imposed on the design for PIO and MDMA
modes.
Multi-word DMA Write to IDE Controller:
The DMAide signal deassertion is generated based on the AHB write logic. The act of writing
to the Multi-word DMA write-FIFO causes the deassertion to appear on the following bus
cycle.
Multi-word DMA Read from IDE Controller:
The DMAide signal deassertion is generated based on the AHB read logic. The act of
reading from the Multi-word DMA read-FIFO causes the deassertion to appear on the
following bus cycle.
Ultra DMA Write to IDE Controller:
The DMAide signal deassertion is generated based on the contents of the Ultra DMA write
FIFO. If the FIFO contains four or more elements, the DMAide signal deasserts.
Ultra DMA Read from IDE Controller:
The DMAide signal deassertion is generated based on an internal counter. The DMAide
signal will deassert if four DMA reads have occurred or if the FIFO is now empty (which only
occurs at the end of a non-quad word aligned read from the IDE device)
The IDE controller requires a certain number of cycles to deassert the DMA request line
DMAide after a DMA access for Multi-word DMA and Ultra DMA modes. The number of wait-
states required are listed below in addition to the pipeline breakdown of the signal
propagation. The assumption is that the deassertion should follow an AHB bus command
(read or write) in HCLK cycle 1.
UDMA Speed Mode
0
1
2
3
4
Table 27-2. IDE Cycle Times and Data Transfer Rates
Min. IDE Cycle Time
Copyright 2007 Cirrus Logic
112 ns
73 ns
54 ns
39 ns
25 ns
Max. AHB Cycle
74.7 ns
48.7 ns
36.0 ns
26.0 ns
16.7 ns
Time
Min. AHB Clock
Frequency
13.4 MHz
20.5 MHz
27.8 MHz
38.5 MHz
59.8 MHz
EP93xx User’s Guide
IDE Interface
27-7
27
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