EP9301-CQ Cirrus Logic Inc, EP9301-CQ Datasheet - Page 387
![IC ARM920T MCU 166MHZ 208-LQFP](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-CQ
Manufacturer Part Number
EP9301-CQ
Description
IC ARM920T MCU 166MHZ 208-LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets
1.EDB9301.pdf
(5 pages)
2.EDB9301.pdf
(4 pages)
3.EP9307-CRZ.pdf
(824 pages)
4.EP9301-IQ.pdf
(41 pages)
Specifications of EP9301-CQ
Core Processor
ARM9
Core Size
16/32-Bit
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
598-1248
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUS
Quantity:
3 390
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUSLOGIC
Quantity:
20 000
Company:
Part Number:
EP9301-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
- EDB9301 PDF datasheet
- EDB9301 PDF datasheet #2
- EP9307-CRZ PDF datasheet #3
- EP9301-IQ PDF datasheet #4
- Current page: 387 of 824
- Download datasheet (13Mb)
RXBufThrshld
DS785UM1
31
15
Definition:
Bit Descriptions:
Address:
Suggested Value:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
Note: There are other reasons to schedule bus transfers other than reaching the threshold. One
30
14
of these is when an end of frame is received. The lower 2 bits of each threshold are always
zero.
29
13
RSVD
RSVD
28
12
Transmit Status Queue Current Address. The Transmit Status Queue Current
Address contains the address being used to transfer transmit status to the
queue. This register is available for debugging.
TSQCA:
0x8001_00D0 - Read/Write
0x0080_0040
0x0000_0000
Unchanged
Receive Buffer Threshold register. The receive buffer thresholds are used to
set a limit on the amount of receive data which is held in the receive data FIFO
before a bus request will be scheduled. When the number of words in the
FIFO exceeds the threshold value, the Descriptor Processor will schedule a
bus request to transfer data. The actual posting of the bus request may be
delayed due to lack of resources in the MAC, such as no active receive
descriptor.
RSVD:
0:
RDHT:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Transmit Status Queue Current Address.
Reserved. Unknown During Read.
Must be written as “0”.
Receive Data Hard Threshold.
24
8
23
7
22
6
RDHT
RDST
21
1/10/100 Mbps Ethernet LAN Controller
5
20
4
19
3
EP93xx User’s Guide
18
2
17
0
1
0
16
9-85
0
0
0
9
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