CY8C26643-24AI Cypress Semiconductor Corp, CY8C26643-24AI Datasheet - Page 26

• Manufacturer Part Number: CY8C26643-24AI
• Description: IC MCU 16K FLASH 256B 44LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ CY8C26xxxr

Specifications of CY8C26643-24AI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.25 V
• Data Converters: A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 428-1431; 428-1431-5; 428-1431

3.0
3.1
Table 24:
26
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
0x0040
0x3FFF
Address
Memory Organization
Flash Program Memory
Organization
Flash Program Memory Map
Reset Vector
Supply Monitor Interrupt Vector
DBA 00 PSoC Block Interrupt Vector
DBA 01 PSoC Block Interrupt Vector
DBA 02 PSoC Block Interrupt Vector
DBA 03 PSoC Block Interrupt Vector
DCA 04 PSoC Block Interrupt Vector
DCA 05 PSoC Block Interrupt Vector
DCA 06 PSoC Block Interrupt Vector
DCA 07 PSoC Block Interrupt Vector
Analog Column 0 Interrupt Vector
Analog Column 1 Interrupt Vector
Analog Column 2 Interrupt Vector
Analog Column 3 Interrupt Vector
GPIO Interrupt Vector
Sleep Timer Interrupt Vector
On-Chip User Program Memory Starts
Here
***
***
***
16K Flash Maximum Depending on Ver-
sion
Description
Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
3.2
The stack on this device grows from low addresses to
high addresses. The Linker function within PSoC
Designer locates the bottom of the stack after the end of
Global Variables. This allows the stack to grow from just
after the Global Variables until 0xFF. The stack will wrap
back to 0x00 on an overflow condition.
Table 25:
4.0
4.1
There are two register banks implemented on these
devices. Each bank contains 256 addresses. The pur-
pose of these register banks is to personalize and
parameterize the on-chip resources as well as read and
write data values.
The user selects between the two banks by setting the
XIO bit in the CPU_F Flag Register.
In some cases, the same register is available on either
bank, for convenience. These registers (71h to 9fh) can
be accessed from either bank.
Note: All register addresses not shown are reserved and
should never be written. In addition, unused or reserved
bits in any register should always be written to 0.
0x00
0xXX
0xXY
0xXZ
0xYX
0xYY
0xFF
Address
RAM Data Memory Organization
Register Organization
Introduction
RAM Data Memory Map
First General Purpose RAM Location
General Purpose RAM
General Purpose RAM
Last General Purpose RAM Location
Bottom of Hardware Stack
Top of Hardware Stack
Stack Grows This Way
Description
September 5, 2002