CY8C26643-24AI Cypress Semiconductor Corp, CY8C26643-24AI Datasheet - Page 57

• Manufacturer Part Number: CY8C26643-24AI
• Description: IC MCU 16K FLASH 256B 44LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ CY8C26xxxr

Specifications of CY8C26643-24AI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.25 V
• Data Converters: A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 428-1431; 428-1431-5; 428-1431

9.3.4
Table 56:
Digital Communications Type A 04 Control Register 0
Digital Communications Type A 05 Control Register 0
Digital Communications Type A Block 06 Control Register 0
Digital Communications Type A Block 07 Control Register 0
September 5, 2002
Bit 7 : Reserved
Bit 6 : Reserved
Bit 5 : TX Complete
0 = Indicates that if a transmission has been initiated, it is still in progress
1 = Indicates that the current transmission is complete (including framing bits)
Optional interrupt source for TX UART. Reset when this register is read.
Bit 4 : TX Reg Empty
0 = Indicates TX Data register is not available to accept another byte (writing to register will cause data to be lost)
1 = Indicates TX Data register is available to accept another byte
Note that the interrupt does not occur until at least 1 byte has been previously written to the TX Data Register
Default interrupt source for TX UART. Reset when the TX Data Register (Data Register 1) is written.
Bit 3 : Reserved
Bit 2 : Parity Type
0 = Even
1 = Odd
Bit 1 : Parity Enable
0 = Parity Disabled
1 = Parity Enabled
Bit 0 : Enable
0 = Function Disabled
1 = Function Enabled
Bit Name
Read/
Write
Bit #
POR
Digital Communications Type A Block xx Control Register 0 When Used as UART Trans-
mitter
Digital Communications Type A Block xx Control Register 0...
Reserved
--
7
0
Reserved
--
6
0
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
TX Complete
R
5
0
TX Reg
Empty
R
4
0
(DCA04CR0, Address = Bank 0, 33h)
(DCA05CR0, Address = Bank 0, 37h)
(DCA06CR0, Address = Bank 0, 3Bh)
(DCA07CR0, Address = Bank 0, 3Fh)
Reserved
--
3
0
Parity Type
RW
2
0
Enable
Parity
RW
Digital PSoC Blocks
1
0
Enable
RW
0
0
57