CY8C26643-24AI Cypress Semiconductor Corp, CY8C26643-24AI Datasheet - Page 68

• Manufacturer Part Number: CY8C26643-24AI
• Description: IC MCU 16K FLASH 256B 44LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ CY8C26xxxr

Specifications of CY8C26643-24AI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.25 V
• Data Converters: A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 428-1431; 428-1431-5; 428-1431

3.
9.5.8.2
Data Register 0 provides a shift register for both incom-
ing and outgoing data. Output data is written to Data
Register 1 (TX Data Register). When this block is idle, a
write to the TX Data Register will initiate a transmission.
Input data is read from Data Register 2 (RX Data Regis-
ter). When Data Register 0 is empty, its value is updated
from Data Register 1, if new data is available. As data
bits are shifted in, the transmit bits are shifted out. After
the 8 bits are transmitted and received by Data Register
68
except for TX Reg Empty. TX Reg Empty is auto-
matically cleared when a byte is written to the TX
Data Register (Data Register 1).
Using CPU Interrupts
TX Reg Empty status or optionally TX Complete sta-
tus generates the block interrupt. Executing the
interrupt routine does not automatically clear status.
If TX Complete is selected as the interrupt source,
Control Register 0 (status) must be read in the inter-
rupt routine to clear the status. If TX Reg Empty is
selected, a byte must be written to the TX Data Reg-
ister (Data Register 1) to clear the status. If the sta-
tus is not cleared, further interrupts will be
suppressed.
SS_
SCLK
SS_
Clock Phase 0 (Mode 0, 1)
Data registered on the leading edge of the clock
Data output on the trailing edge of the clock
MOSI/MISO
SCLK
Clock Phase 1 (Mode 2, 3)
Data output on the leading edge of the clock
Data registered on the trailing edge of the clock
MOSI/MISO
Registers
(required f or slav e)
(optional f or slav e)
Polarity=0, Mode 0
Polarity=1, Mode 1
Polarity=0, Mode 2
Polarity=1, Mode 3
Bit7
Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
Bit7
Bit6
Figure 15: SPI Waveforms
Bit6
Bit5
Bit5
Bit4
9.5.8
9.5.8.1
The SPI Master function provides a full-duplex synchro-
nous data transceiver that also generates a bit clock for
the data. This function requires a Digital Communica-
tions Type PSoC block. It cannot be chained for longer
data words. This Digital Communications Type PSoC
block supports SPI modes for 0, 1, 2, and 3. See
Title 15
0, the received byte is transferred into Data Register 2
from where it can be read. Simultaneously, the next byte
to transmit, if available, is transferred from Data Register
1 into Data Register 0. Control Register 0 (DCA04CR0-
DCA07CR0) provides status information and configures
the function for one of the four standard modes, which
configure the interface based on clock polarity and
phase with respect to data.
Bit4
Bit3
for waveforms of the Clock Phase modes.
SPI Master - Serial Peripheral Interface
(SPIM)
Bit3
Summary
Bit2
Bit2
Bit1
Bit1
Bit0
Bit0
September 5, 2002
Bit7
Figure-