CY8C26643-24AI Cypress Semiconductor Corp, CY8C26643-24AI Datasheet - Page 29

• Manufacturer Part Number: CY8C26643-24AI
• Description: IC MCU 16K FLASH 256B 44LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ CY8C26xxxr

Specifications of CY8C26643-24AI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.25 V
• Data Converters: A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 428-1431; 428-1431-5; 428-1431

5.0
5.1
Up to five 8-bit-wide I/O ports (P0-P4) and one 4-bit wide
I/O port (P5) are implemented. The number of general
purpose I/Os implemented and connected to pins
depends on the individual part chosen. All port bits are
independently programmable and have the following
capabilities:
S
S
S
S
S
S
Port 1, pin 0 is used in conjunction with device Test
Mode and will not function as an output for approxi-
mately 16 ms after X
will be held low for approximately 16 ms. This does not
prevent the CPU from writing to this Data Register bit
(PRT0DR, bit 0). However, the written data will not
appear on the output pin until after the 16 ms delay.
There are no restrictions when using the pin as an input.
In addition, the pin may also be configured (e.g., drive
September 5, 2002
General-purpose digital input readable by the CPU.
General-purpose digital output writable by the CPU.
Independent control of data direction for each port
bit.
Independent access for each port bit to Global Input
and Global Output busses.
Interrupt programmable to assert on rising edge,
falling edge, or change from last pin state read.
Output drive strength programmable in logic 0 and 1
states as strong, resistive (pull-up or pull-down), or
high impedance.
I/O Ports
Introduction
RES
. After negating X
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
RES
, the pin
strength, interrupts) during this time. A device reset with
Power On Reset (POR) will not exhibit this problem
because there is a CPU hold-off time of approximately
64 ms before code execution begins.
In System Sleep State, GPIO Pins P2[4] and P2[6]
should be held to a logic low or a false Low Voltage
Detect interrupt may be triggered. The cause is in the
System Sleep State, the internal Bandgap reference
generator is turned off and the reference voltage is main-
tained on a capacitor.
The circumstances are that during sleep, the reference
voltage on the capacitor is refreshed periodically at the
sleep system duty cycle. Between refresh cycles, this
voltage may leak slightly to either the positive supply or
ground. If pins P2[4] or P2[6] are in a high state, the leak-
age to the positive supply is accelerated (especially at
high temperature). Since the reference voltage is com-
pared to the supply to detect a low voltage condition, this
accelerated leakage to the positive supply voltage will
cause that voltage to appear lower than it actually is,
leading to the generation of a false Low Voltage Detect
interrupt.
Port 0 and Port 2 have additional analog input and/or
analog output capability. The specific routing and multi-
plexing of analog signals is shown in the following dia-
gram:
I/O Ports
29