Z8F0812SJ020EC Zilog, Z8F0812SJ020EC Datasheet - Page 116

• Manufacturer Part Number: Z8F0812SJ020EC
• Description: IC ENCORE MCU FLASH 8K 28SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0812SJ020EC

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-3228

Table 56. UART Control 0 Register (U0CTL0)
PS022517-0508
BITS
FIELD
RESET
R/W
ADDR
UART Control 0 and Control 1 Registers
TEN
7
Reserved—Must be 0
NEWFRM—Status bit denoting the start of a new frame. Reading the UART Receive
Data Register resets this bit to 0.
0 = The current byte is not the first data byte of a new frame.
1 = The current byte is the first data byte of a new frame.
MPRX—Multiprocessor Receive
Returns the value of the last multiprocessor bit received. Reading from the UART Receive
Data Register resets this bit to 0.
The UART Control 0 and Control 1 registers
ure the properties of the UART’s transmit and receive operations. The UART Control
Registers must not been written while the UART is enabled.
TEN—Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSE bit. If the CTS signal is low and the CTSE bit is 1, the transmitter is
enabled.
0 = Transmitter disabled.
1 = Transmitter enabled.
REN—Receive Enable
This bit enables or disables the receiver.
0 = Receiver disabled.
1 = Receiver enabled.
CTSE—CTS Enable
0 = The CTS signal has no effect on the transmitter.
1 = The UART recognizes the CTS signal as an enable control from the transmitter.
PEN—Parity Enable
This bit enables or disables parity. Even or odd is determined by the PSEL bit. This bit is
overridden by the
0 = Parity is disabled.
1 = The transmitter sends data with an additional parity bit and the receiver
receives an additional parity bit.
REN
6
MPEN
CTSE
5
bit.
PEN
4
F42H
R/W
0
PSEL
(Table 56
3
Universal Asynchronous Receiver/Transmitter
and
Z8 Encore! XP
SBRK
2
Table 57
Product Specification
on page 104) config-
STOP
1
®
F0822 Series
LBEN
0
103