Z8F0812SJ020EC Zilog, Z8F0812SJ020EC Datasheet - Page 118
Z8F0812SJ020EC
Manufacturer Part Number
Z8F0812SJ020EC
Description
IC ENCORE MCU FLASH 8K 28SOIC
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheet
1.Z8F08200100KIT.pdf
(264 pages)
Specifications of Z8F0812SJ020EC
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
269-3228
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PS022517-0508
UART Address Compare Register
MPBT—Multiprocessor Bit Transmit
This bit is applicable only when Multiprocessor (9-bit) mode is enabled.
0 = Send a 0 in the multiprocessor bit location of the data stream (9th bit).
1 = Send a 1 in the multiprocessor bit location of the data stream (9th bit).
DEPOL—Driver Enable Polarity
0 = DE signal is Active High.
1 = DE signal is Active Low.
BRGCTL—Baud Rate Control
This bit causes different UART behavior depending on whether the UART receiver is
enabled (REN = 1 in the UART Control 0 Register).
When the UART receiver is not enabled, this bit determines whether the BRG will issue
interrupts.
0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value
1 = The BRG generates a receive interrupt when it counts down to
When the UART receiver is enabled, this bit allows reads from the Baud Rate Registers to
return the BRG count value instead of the Reload Value.
0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value.
1 = Reads from the Baud Rate High and Low Byte registers return the current BRG
RDAIRQ—Receive Data Interrupt Enable
0 = Received data and receiver errors generates an interrupt request to the
1 = Received data does not generate an interrupt request to the Interrupt Controller.
IREN—Infrared Encoder/Decoder Enable
0 = Infrared Encoder/Decoder is disabled. UART operates normally operation.
1 = Infrared Encoder/Decoder is enabled. The UART transmits and receives data
The UART Address Compare register stores the multi-node network address of the UART.
When the MPMD[1] bit of UART Control Register 0 is set, all incoming address bytes
will be compared to the value stored in the Address Compare register. Receive
interrupts and RDA assertions will only occur in the event of a match.
Interrupt Controller.
zero. Reads from the Baud Rate High and Low Byte registers return the current
BRG count value.
count value. Unlike the Timers, there is no mechanism to latch the High Byte
Only receiver errors generate an interrupt request.
through the Infrared Encoder/Decoder.
when the Low Byte is read.
Universal Asynchronous Receiver/Transmitter
Z8 Encore! XP
Product Specification
®
F0822 Series
105
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