Z8F0812SJ020EC Zilog, Z8F0812SJ020EC Datasheet - Page 98
![IC ENCORE MCU FLASH 8K 28SOIC](/photos/6/91/69136/269-28-soic_sml.jpg)
Z8F0812SJ020EC
Manufacturer Part Number
Z8F0812SJ020EC
Description
IC ENCORE MCU FLASH 8K 28SOIC
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheet
1.Z8F08200100KIT.pdf
(264 pages)
Specifications of Z8F0812SJ020EC
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
269-3228
- Current page: 98 of 264
- Download datasheet (6Mb)
PS022517-0508
Watchdog Timer Reload Unlock Sequence
WDT Reset in Normal Operation
If configured to generate a Reset when a time-out occurs, the WDT forces the device into
the Reset state. The WDT status bit in the WDT Control Register is set to 1. For more infor-
mation on Reset, see
WDT Reset in STOP Mode
If enabled in STOP mode and configured to generate a Reset when a time-out occurs
and the device is in STOP mode, the WDT initiates a Stop Mode Recovery. Both the
WDT status bit and the STOP bit in the WDT Control Register is set to 1 following
WDT time-out in STOP mode. For more information on Reset, see
Recovery
during STOP mode.
WDT RC Disable in STOP Mode
To minimize power consumption in STOP mode, the WDT and its RC oscillator can be
disabled in STOP mode. The following sequence configures the WDT to be disabled when
the Z8F082x family device enters STOP mode following execution of a
1. Write
2. Write
3. Write
Writing the unlock sequence to the WDTCTL address unlocks the three Watchdog Timer
Reload Byte Registers (WDTU, WDTH, and WDTL) to allow changes to the time-out
period. These write operations to the WDTCTL address produce no effect on the bits in
the WDTCTL. The locking mechanism prevents spurious writes to the Reload Registers.
The following sequence is required to unlock the Watchdog Timer Reload Byte Registers
(WDTU, WDTH, and WDTL) for write access.
1. Write
2. Write
3. Write the Watchdog Timer Reload Upper Byte Register (WDTU).
4. Write the Watchdog Timer Reload High Byte Register (WDTH).
5. Write the Watchdog Timer Reload Low Byte Register (WDTL).
and its oscillator to be disabled during STOP mode. Alternatively, write
Watchdog Timer Control Register (WDTCTL) as the third step in this sequence to
reconfigure the WDT and its oscillator to be enabled during STOP mode. This
sequence only affects WDT operation in STOP mode.
on page 39. Default operation is for the WDT and its RC oscillator to be enabled
81H
55H
AAH
55H
AAH
to the Watchdog Timer Control Register (WDTCTL) to configure the WDT
to the Watchdog Timer Control Register (WDTCTL).
to the Watchdog Timer Control Register (WDTCTL).
to the Watchdog Timer Control Register (WDTCTL).
to the Watchdog Timer Control Register (WDTCTL).
Reset and Stop Mode Recovery
on page 39.
Z8 Encore! XP
Product Specification
Reset and Stop Mode
STOP
®
F0822 Series
Watchdog Timer
00H
instruction:
to the
85
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