UPSD3433E-40T6 STMicroelectronics, UPSD3433E-40T6 Datasheet - Page 248

• Manufacturer Part Number: UPSD3433E-40T6
• Description: MCU 8BIT 8032 128KB FLASH 52TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40T6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-TQFP, 52-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4906

PSD module
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Note:
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Power management
The PSD module offers configurable power saving options. These options may be used
individually or in combinations. A top level description for these functions is given here, then
more detailed descriptions will follow.
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Non-address signals are still available to PLD inputs and will wake up the PLDs if these
signals are changing state, but will not wake up the memories.
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Zero-Power memory: All memory arrays (Flash and SRAM) in the PSD module are
built with zero-power technology. It puts the Flash memory into standby mode (~ zero
DC current) when 8032 address signals are not changing. As soon as a transition
occurs on any address input, the Flash memory “wakes up”, changes and latches its
outputs, then goes back to standby. The designer does not have to do anything special
to achieve this memory standby mode when no inputs are changing—it happens
automatically. Thus, the slower the 8032 clock, the lower the current consumption.
Both PLDs (DPLD and GPLD) are also zero-power, but this is not the default condition.
The 8032 must set a bit in one of the csiop PMMR registers at run-time to achieve zero-
power.
Automatic Power-down (APD): The APD feature allows the PSD module to reach its
lowest current consumption levels. If enabled, the APD counter will time-out when there
is a lack of 8032 bus activity for an extended amount of time (8032 asleep). After time-
out occurs, all 8032 address and data buffers on the PSD module are shut down,
preventing the PSD module memories and potentially the PLDs from waking up from
standby, even if address inputs are changing state because of noise or any external
components driving the address lines. Since the actual address and data buffers are
turned off, current consumption is even further reduced.
The APD counter requires a relatively slow external clock input on pin PD1 that does
stop when the 8032 goes to sleep mode.
Forced Power-down (FPD): The MCU can put the PSD module into Power-Down
mode with the same results as using APD described above, but FPD does not rely on
the APD counter. Instead, FPD will force the PSD module into Power-Down mode when
the MCU firmware sets a bit in one of the csiop PMMR registers. This is a good
alternative to APD because no external clock is needed for the APD counter.
PSD module Chip Select input (CSI): This input on pin PD2 (80-pin devices only) can
be used to disable the internal Flash memory, placing it in standby mode even if
address inputs are changing. This feature does not block any internal signals (the
address and data buffers are still on but signals are ignored) and CSI does not disable
the PLDs. This is a good alternative to using the APD counter, which requires an
external clock on pin PD1.
Non-Turbo mode: The PLDs can operate in Turbo or non-Turbo modes. Turbo mode
has the shortest signal propagation delay, but consumes more current than non-Turbo
mode. A csiop register can be written by the 8032 to select modes, the default mode is
with Turbo mode enabled. In non-Turbo mode, the PLDs can achieve very low standby
current (~ zero DC current) while no PLD inputs are changing, and the PLDs will even
use less AC current when inputs do change compared to Turbo mode.
When the Turbo mode is enabled, there is a significant DC current component AND the
AC current component is higher than non-Turbo mode, as shown in
page 265
Blocking bits: Significant power savings can be achieved by blocking 8032 bus control
signals (RD, WR, PSEN, ALE) from reaching PLD inputs, if these signals are not used
in any PLD equations. Blocking is achieved by the 8032 writing to the “blocking bits” in
(5 V) and
Figure 96 on page 266
UPSD3422, UPSD3433, UPSD3434, UPSD3454
(3.3 V).
Figure 95 on