UPSD3433E-40T6 STMicroelectronics, UPSD3433E-40T6 Datasheet - Page 258
UPSD3433E-40T6
Manufacturer Part Number
UPSD3433E-40T6
Description
MCU 8BIT 8032 128KB FLASH 52TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet
1.UPSD3422EV-40U6.pdf
(300 pages)
Specifications of UPSD3433E-40T6
Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
160KB (160K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-TQFP, 52-VQFP
For Use With
497-5518 - EVAL BOARD RFID READER
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-4906
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
UPSD3433E-40T6
Manufacturer:
STMicroelectronics
Quantity:
10 000
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PSD module
28.6.3
258/300
PSD module is in BYPASS mode while debugging the MCU module, and the MCU module
is in BYPASS mode while performing ISP on the PSD module.
The RESET_IN input pin on the UPSD34xx package goes to the MCU module, and this
module will generate the RST reset signal for the PSD module. These reset signals are
totally independent of the JTAG TAP controllers, meaning that the JTAG channel is
operational when the modules are held in reset. It is required to assert RESET_IN during
ISP. STMicroelectronics and 3rd party JTAG ISP tools will automatically assert a reset signal
during ISP. However, the user must connect this reset signal to RESET_IN as shown in
examples in
Figure 90. JTAG chain in UPSD34xx package
In-system programming
The ISP function can use two different configurations of the JTAG interface:
●
●
At power-up, the four basic JTAG signals are all inputs, waiting for a command to appear on
the JTAG bus from programming or test equipment. When the enabling command is
received, TDO becomes an output and the JTAG channel is fully functional. The same
command that enables the JTAG channel may optionally enable the two additional signals,
TSTAT and TERR.
4-pin JTAG: TDI, TDO, TCK, TMS
6-pin JTAG: Signals above plus TSTAT, TERR
Figure 91 on page 259
PC3 / TSTAT
OPTIONAL
IEEE 1149.1
PC4 / TERR
OPTIONAL
RESET_IN
JTAG TDO
JTAG TMS
JTAG TCK
JTAG TDI
DEBUG
and
MCU MODULE
PSD MODULE
Figure 92 on page
TSTAT
TERR
MEMORY
FLASH
UPSD3422, UPSD3433, UPSD3434, UPSD3454
MAIN
TDO
TDI
MEMORY
TMS TCK
TMS TCK
FLASH
2ND
CONTROLLER
CONTROLLER
8032 MCU
JTAG TAP
JTAG TAP
PLD
TDI
TDO
RESET
uPSD34xx
261.
RST
AI10460
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