UPSD3433E-40T6 STMicroelectronics, UPSD3433E-40T6 Datasheet - Page 260

• Manufacturer Part Number: UPSD3433E-40T6
• Description: MCU 8BIT 8032 128KB FLASH 52TQFP
• Manufacturer: STMicroelectronics
• Series: µPSDr

Specifications of UPSD3433E-40T6

• Core Processor: 8032
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 160KB (160K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-TQFP, 52-VQFP
• For Use With: 497-5518 - EVAL BOARD RFID READER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-4906

PSD module
28.6.5
Note:
260/300
6-pin JTAG ISP (optional)
The optional signals TSTAT and TERR are programming status flags that can reduce
programming time by as much as 30% compared to 4-pin JTAG because this status
information does not have to be scanned out of the device serially. TSTAT and TERR must
be used as a pair for 6-pin JTAG operation.
●
●
The pin functions for PC3 and PC4 must be selected as “Dedicated JTAG - TSTAT” and
“Dedicated JTAG - TERR” in PSDsoft Express to enable 6-pin JTAG ISP.
No 8032 firmware is needed to use 6-pin ISP because all ISP functions are controlled from
the external JTAG program/test equipment.
TSTAT and TERR are functional only when JTAG ISP operations are occurring, which
means they are non-functional during JTAG debugging of the 8032 on the MCU module.
Programming times vary depending on the number of locations to be programmed and the
JTAG programming equipment, but typical JTAG ISP programming times are 10 to 25
seconds using 6-pin JTAG. The signals TSTAT and TERR are not included in the IEEE
1149.1 specification.
Figure 92 on page 261
program/test tool using 6-pin JTAG. It is required to connect the RST output signal from the
JTAG program/test equipment to the RESET_IN input on the UPSD34xx. The RST signal is
driven by the equipment with an Open Drain driver, allowing other sources (like a push
button) to drive RESET_IN without conflict.
The recommended pull-up resistors and decoupling capacitor are illustrated in
TSTAT (pin PC3) indicates when programming of a single Flash location is complete.
Logic 1 = Ready, Logic 0 = busy.
TERR (pin PC4) indicates if there was a Flash programming error. Logic 1 = no error,
Logic 0 = error.
shows recommended connections on a circuit board to a JTAG
UPSD3422, UPSD3433, UPSD3434, UPSD3454
Figure
92.