ST7FMC1K2B6 STMicroelectronics, ST7FMC1K2B6 Datasheet - Page 120

MCU 8BIT 8K FLASH 32DIP

ST7FMC1K2B6

Manufacturer Part Number
ST7FMC1K2B6
Description
MCU 8BIT 8K FLASH 32DIP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST7FMC1K2B6

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
LINSCI
Peripherals
LVD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-DIP (0.600", 15.24mm)
For Use With
497-8402 - BOARD EVAL COMPLETE INVERTER497-8400 - KIT IGBT PWR MODULE CTRL ST7MC497-4734 - EVAL KIT 3KW POWER DRIVER BOARD497-4733 - EVAL KIT 1KW POWER DRIVER BOARD497-4732 - EVAL KIT 300W POWER DRIVER BOARD497-4731 - EVAL KIT PWR DRIVER CONTROL BRD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-4864
ST7MC1xx/ST7MC2xx
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
BAUD RATE REGISTER (SCIBRR)
Read/Write
Reset Value: 0000 0000 (00h)
Note: When LIN slave mode is disabled, the SCI-
BRR register controls the conventional baud rate
generator.
Bits 7:6 = SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 and
SCP0 bits define the total division applied to the
bus clock to yield the transmit rate clock in conven-
tional Baud Rate Generator mode.
120/309
1
SCP1
7
PR Prescaling factor
SCP0
13
SCT2
1
3
4
SCT1
SCT0
SCP1
SCR2 SCR1 SCR0
0
1
SCP0
0
1
0
1
0
Bits 2:0 = SCR[2:0] SCI Receiver rate divider
These 3 bits, in conjunction with the SCP[1:0] bits
define the total division applied to the bus clock to
yield the receive rate clock in conventional Baud
Rate Generator mode.
RR dividing factor
TR dividing factor
128
128
16
32
64
16
32
64
1
2
4
8
1
2
4
8
SCR2
SCT2
0
1
0
1
SCR1
SCT1
0
1
0
1
0
1
0
1
SCR0
SCT0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

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