MC68HC908GT8CFB Freescale Semiconductor, MC68HC908GT8CFB Datasheet - Page 214

• Manufacturer Part Number: MC68HC908GT8CFB
• Description: IC MCU 8K FLASH 8MHZ 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GT8CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 34
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Serial Peripheral Interface (SPI) Module
SPWOM — SPI Wired-OR Mode Bit
SPE — SPI Enable
SPTIE— SPI Transmit Interrupt Enable
16.12.2 SPI Status and Control Register
The SPI status and control register contains flags to signal these conditions:
The SPI status and control register also contains bits that perform these functions:
SPRF — SPI Receiver Full Bit
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This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins
become open-drain outputs.
This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. (See
Resetting the
This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte
transfers from the transmit data register to the shift register. Reset clears the SPTIE bit.
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This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data
register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register
with SPRF set and then reading the SPI data register.
Reset clears the SPRF bit.
1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins
1 = SPI module enabled
0 = SPI module disabled
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
1 = Receive data register full
0 = Receive data register not full
Receive data register full
Failure to clear SPRF bit before next byte is received (overflow error)
Inconsistent logic level on SS pin (mode fault error)
Transmit data register empty
Enable error interrupts
Enable mode fault error detection
Select master SPI baud rate
Address: $0011
Reset:
Read:
Write:
SPI.) Reset clears the SPE bit.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Figure 16-15. SPI Status and Control Register (SPSCR)
SPRF
Bit 7
0
= Unimplemented
ERRIE
6
0
OVRF
5
0
MODF
4
0
SPTE
3
1
MODFEN
2
0
SPR1
1
0
Freescale Semiconductor
SPR0
Bit 0
0
16.8