MC68HC908GT8CFB Freescale Semiconductor, MC68HC908GT8CFB Datasheet - Page 237

• Manufacturer Part Number: MC68HC908GT8CFB
• Description: IC MCU 8K FLASH 8MHZ 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GT8CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 34
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Chapter 19
Development Support
19.1 Introduction
This section describes the break module, the monitor module (MON), and the monitor mode entry
methods.
19.2 Break Module (BRK)
This section describes the break module (BRK). The break module can generate a break interrupt that
stops normal program flow at a defined address to enter a background program.
Features of the break module include:
19.2.1 Functional Description
When the internal address bus matches the value written in the break address registers, the break module
issues a breakpoint signal to the system integration module (SIM). The SIM then causes the CPU to load
the instruction register with a software interrupt instruction (SWI). The program counter vectors to $FFFC
and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
When a CPU generated address matches the contents of the break address registers, the break interrupt
is generated. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and
returns the microcontroller unit (MCU) to normal operation.
module.
Freescale Semiconductor
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Accessible input/output (I/O) registers during the break interrupt
Central processor unit (CPU) generated break interrupts
Software-generated break interrupts
Computer operating properly (COP) disabling during break interrupts
A CPU generated address (the address in the program counter) matches the contents of the break
address registers.
Software writes a 1 to the BRKA bit in the break status and control register.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Figure 19-2
shows the structure of the break
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