MC68HC908GT8CFB Freescale Semiconductor, MC68HC908GT8CFB Datasheet - Page 55

• Manufacturer Part Number: MC68HC908GT8CFB
• Description: IC MCU 8K FLASH 8MHZ 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GT8CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 34
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

ADCH4–ADCH0 — ADC Channel Select Bits
The voltage levels supplied from internal reference nodes, as specified in
Table
applications.
3.7.2 ADC Data Register
One 8-bit result register, ADC data register (ADR), is provided. This register is updated each time an ADC
conversion completes.
Freescale Semiconductor
ADCH4–ADCH0 form a 5-bit field which is used to select one of 16 ADC channels. Only eight
channels, AD7–AD0, are available on this MCU. The channels are detailed in
be taken when using a port pin as both an analog and digital input simultaneously to prevent switching
noise from corrupting the analog signal. See
The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for
reduced power consumption for the MCU when the ADC is not being used.
3-1, are used to verify the operation of the ADC converter both in production test and for user
Address:
1. If any unused channels are selected, the resulting ADC conversion will be unknown or
Recovery from the disabled state requires one conversion cycle to stabilize.
ADCH4
Reset:
Read:
Write:
reserved.
0
0
0
0
0
0
0
0
0
↓
1
1
1
1
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
$003D
Bit 7
AD7
0
ADCH3
↓
0
0
0
0
0
0
0
0
1
1
1
1
1
= Unimplemented
Figure 3-4. ADC Data Register (ADR)
AD6
6
0
Table 3-1. Mux Channel Select
ADCH2
0
0
0
0
1
1
1
1
0
↓
1
1
1
1
AD5
5
0
Table
ADCH1
NOTE
AD4
↓
0
0
1
1
0
0
1
1
0
0
0
1
1
4
0
3-1.
AD3
ADCH0
3
0
0
1
0
1
0
1
0
1
0
↓
0
1
0
1
(1)
AD2
2
0
ADC power off
Input Select
PTB0/AD0
PTB1/AD1
PTB1/AD2
PTB2/AD3
PTB4/AD4
PTB5/AD5
PTB6/AD6
PTB7/AD7
Reserved
V
V
AD1
REFH
1
0
REFL
Table
Bit 0
AD0
3-1. Care should
0
I/O Registers
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