MC68HC908LJ12CFU Freescale Semiconductor, MC68HC908LJ12CFU Datasheet - Page 138

• Manufacturer Part Number: MC68HC908LJ12CFU
• Description: IC MCU 12K FLASH 8MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908LJ12CFU

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: IRSCI, SPI
• Peripherals: LCD, LVD, POR, PWM
• Number Of I /o: 32
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

System Integration Module (SIM)
9.4.2.1 Power-On Reset
Technical Data
138
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power-on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 + 32 ICLK cycles. Thirty-two ICLK cycles later, the CPU and
memories are released from reset to allow the reset vector sequence to
occur.
At power-on, these events occur:
•
•
•
•
•
•
IRST
ICLK
RST
IAB
A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables CGMOUT.
Internal clocks to the CPU and modules are held inactive for 4096
ICLK cycles to allow stabilization of the oscillator.
The RST pin is driven low during the oscillator stabilization time.
The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared.
System Integration Module (SIM)
ILLEGAL ADDRESS RST
Figure 9-6. Sources of Internal Reset
ILLEGAL OPCODE RST
RST PULLED LOW BY MCU
Figure 9-5. Internal Reset Timing
COPRST
32 CYCLES
POR
LVI
INTERNAL RESET
32 CYCLES
MC68HC908LJ12
Freescale Semiconductor
VECTOR HIGH
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Rev. 2.1