C8051F302 Silicon Laboratories Inc, C8051F302 Datasheet - Page 135

• Manufacturer Part Number: C8051F302
• Description: IC 8051 MCU 8K FLASH 11MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F302

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 11-VQFN
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

15.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload
Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value.
TL0 holds the count and TH0 holds the reload value. When the counter in TL0 overflows from all ones to 0x00, the
timer overflow flag TF0 (TCON.5) is set and the counter in TL0 is reloaded from TH0. If Timer 0 interrupts are
enabled, an interrupt will occur when the TF0 flag is set. The reload value in TH0 is not changed. TL0 must be initial-
ized to the desired value before enabling the timer for the first count to be correct. When in Mode 2, Timer 1 operates
identically to Timer 0.
Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Setting the TR0 bit
(TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or when the input signal /INT0 is active as
defined by bit IN0PL in register INT01CF (see
external input signals /INT0 and /INT1).
/INT0
T0
Crossbar
Pre-scaled Clock
SYSCLK
IN0PL
GATE0
Figure 15.2. T0 Mode 2 Block Diagram
XOR
0
1
TR0
M
T
2
H
CKCON
M
T
2
L
M
T
1
Section “8.3.2. External Interrupts” on page 68
0
1
M
T
0
S
C
A
1
S
C
A
0
G
A
T
E
1
Rev. 2.3
C
T
1
/
M
T
1
1
TMOD
M
T
1
0
TCLK
G
A
T
E
0
C
T
0
/
M
T
0
1
M
T
0
0
(8 bits)
(8 bits)
TH0
TL0
C8051F300/1/2/3/4/5
N
P
1
L
I
N
S
1
L
2
I
INT01CF
N
S
1
L
1
I
N
1
S
L
0
I
N
P
0
L
I
Reload
N
S
0
L
2
I
N
S
0
L
1
I
N
0
S
L
0
I
TR1
TR0
TF1
TF0
IE1
IE0
IT1
IT0
for details on the
Interrupt
135