C8051F302 Silicon Laboratories Inc, C8051F302 Datasheet - Page 47

• Manufacturer Part Number: C8051F302
• Description: IC 8051 MCU 8K FLASH 11MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F302

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 11-VQFN
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

7.
C8051F300/1/2/3/4/5 devices include an on-chip programmable voltage comparator, which is shown in Figure 7.1.
Comparator0 offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are
optionally available at the Port pins: a synchronous “latched” output (CP0), or an asynchronous “raw” output
(CP0A). The asynchronous CP0A signal is available even when the system clock is not active. This allows
Comparator0 to operate and generate an output with the device in STOP mode. When assigned to a Port pin, the
Comparator0 output may be configured as open drain or push-pull (see
page
The inputs for Comparator0 are selected in the CPT0MX register (Figure 7.4). The CMX0P1-CMX0P0 bits select the
Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0 negative input.
Important Note About Comparator Inputs: The Port pins selected as comparator inputs should be configured as
analog inputs in their associated Port configuration register, and configured to be skipped by the Crossbar (for details
on Port configuration, see
98). Comparator0 may also be used as a reset source (see
CMX0N1
CMX0N0
CMX0P1
CMX0P0
COMPARATOR0
P0.0
P0.2
P0.4
P0.6
P0.1
P0.3
P0.5
P0.7
Figure 7.1. Comparator0 Functional Block Diagram
Section “12.3. General Purpose Port I/O” on page
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CP0OUT
CP0RIF
CP0FIF
CP0EN
CP0 +
CP0 -
CP0MD1
CP0MD0
+
-
Rev. 2.3
VDD
GND
Section “9.5. Comparator0 Reset” on page
Decision
Reset
Tree
Section “12.2. Port I/O Initialization” on
C8051F300/1/2/3/4/5
(SYNCHRONIZER)
D
SET
CLR
Q
Q
101).
D
SET
CLR
Q
Q
Interrupt Flag
Rising-edge
CP0
Crossbar
Interrupt
Logic
Interrupt Flag
Falling-edge
CP0
CP0A
CP0
79).
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