C8051F302 Silicon Laboratories Inc, C8051F302 Datasheet - Page 79

• Manufacturer Part Number: C8051F302
• Description: IC 8051 MCU 8K FLASH 11MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F302

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 8
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 11-VQFN
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, SMBus, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 8
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Important Note: Enabling the VDD monitor will immediately generate a system reset. The device will then return
from the reset state with the VDD monitor enabled. Writing a logic ‘1’ to the PORSF flag when the VDD monitor
is enabled does not cause a system reset.
9.3.
The external /RST pin provides a means for external circuitry to force the device into a reset state. Asserting an
active-low signal on the /RST pin generates a reset; an external pull-up and/or decoupling of the /RST pin may be
necessary to avoid erroneous noise-induced resets. See Table 9.2 for complete /RST pin specifications. The PINRSF
flag (RSTSRC.0) is set on exit from an external reset.
9.4.
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system clock
remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a MCD reset, the
MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source; otherwise, this bit reads ‘0’. Writ-
ing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a ‘0’ disables it. The state of the /RST pin
is unaffected by this reset.
9.5.
Comparator0 can be configured as a reset source by writing a ‘1’ to the C0RSEF flag (RSTSRC.5). Comparator0
should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on chatter on the output from
generating an unwanted reset. The Comparator0 reset is active-low: if the non-inverting input voltage (on CP0+) is
less than the inverting input voltage (on CP0-), the device is put into the reset state. After a Comparator0 reset, the
C0RSEF flag (RSTSRC.5) will read ‘1’ signifying Comparator0 as the reset source; otherwise, this bit reads ‘0’. The
state of the /RST pin is unaffected by this reset.
9.6.
The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be used to pre-
vent software from running out of control during a system malfunction. The PCA WDT function can be enabled or
disabled by software as described in
clocked by SYSCLK / 12 following any reset. If a system malfunction prevents user software from updating the
WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is set to ‘1’. The state of the /RST pin is unaffected by
this reset.
9.7.
If a FLASH read/write/erase or program read targets an illegal address, a system reset is generated. This may occur
due to any of the following:
•
•
•
A FLASH write or erase is attempted above user code space. This occurs when PSWE is set to ‘1’ and a MOVX
operation is attempted above the user code space address limit.
A FLASH read is attempted above user code space. This occurs when a MOVC operation is attempted above the
user code space address limit.
A Program read is attempted above user code space. This occurs when user code attempts to branch to an address
above the user code space address limit.
External Reset
Missing Clock Detector Reset
Comparator0 Reset
PCA Watchdog Timer Reset
FLASH Error Reset
C8051F300/1/2/3
C8051F304
Table 9.1. User Code Space Address Limits
Device
Section “16.3. Watchdog Timer Mode” on page
User Code Space Address Limit
Rev. 2.3
0x1DFF
0x0FFF
C8051F300/1/2/3/4/5
156; the WDT is enabled and
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