MPC564CVR40 Freescale Semiconductor, MPC564CVR40 Datasheet - Page 199

• Manufacturer Part Number: MPC564CVR40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CVR40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

possible interrupt addresses to single-step such instructions. If this is unacceptable, other debug features
can be used. Refer to
Exception register settings.
Execution resumes at offset 0x0D00 from the base address indicated by MSR[IP].
3.15.4.12 Floating-Point Assist Exception (0x0E00)
A floating point assist exception occurs when the following conditions are true:
These conditions are summarized in the following equation:
Note that when ((MSR[FE0] | MSR[FE1]) AND FPSCR[FEX]) is set as a result of move to FPSCR, move
to MSR or rfi, a program exception is generated, rather than a floating-point assist exception.
A floating point assist exception also occurs when a tiny result is detected and the floating point underflow
exception is disabled (FPSCR[UE] = 0).
The register settings for floating-point assist exceptions are shown in
Freescale Semiconductor
1
•
•
•
Save/Restore Register 0 (SRR0)
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
Machine State Register (MSR)
A floating-point enabled exception condition is detected;
The corresponding floating-point enable bit in the FPSCR (floating point status and control
register) is set (exception enabled); and
MSR[FE0] | MSR[FE1] = 1
(MSR[FE0] | MSR[FE1]) AND FPSCR[FEX] = 1
Register Name
Register Name
Table 3-33. Register Settings following Floating-Point Assist Exceptions
Chapter 23, “Development
Table 3-32. Register Settings following a Trace Exception
1
1
MPC561/MPC563 Reference Manual, Rev. 1.2
DCMPEN
10:15
Other
Other
Bits
Bits
ME
1:4
LE
All
All
IP
Support,” for more information. See
Set to the effective address of the instruction following the
executed instruction
Cleared to 0
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
No change
Bit is copied from ILE
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Set to the effective address of the instruction that caused the
interrupt
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
No change
Cleared to 0
Table
Description
Description
3-33.
Table 3-32
Central Processing Unit
for Trace
3-55