HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 818
HD6417760BP200QS
Manufacturer Part Number
HD6417760BP200QS
Description
IC SUPERH MCU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BP200QS
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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(1) Configuration Mode
This mode is entered after the module is released from reset. All required settings in the control
register should be defined in this mode, before the SSI module is enabled by setting the EN bit.
Setting the EN bit causes the SSI module to enter the module enabled mode.
(2) Module Enabled Mode
Operation of the module in this mode depends on the selected operating mode. For details, see
section 20.4.5, Transmit Operation and section 20.4.6, Receive Operation.
20.4.5
Transmission can be controlled in one of two ways: either DMA or an interrupt driven.
DMA driven is preferred to reduce the CPU load. In DMA control mode, an underflow or
overflow of data or DMAC transfer end is notified by using an interrupt.
The alternative is using the interrupts that the SSI module generates to supply data as required.
This mode has a higher interrupt load as the SSI module is only double buffered and will require
data to be written at least every system word period.
When the SSI module has been enabled for transmission, at least one longword must be written to
the transmit register before disabling the transmitter (In 16-bit mode, two 16-bit words will be
transmitted; in 8-bit mode, 4 bytes will be transmitted. For all other data sizes, one data word will
be transmitted, e.g., 18 bits for 18-bit mode.)
Rev. 2.00 Feb. 12, 2010 Page 734 of 1330
REJ09B0554-0200
Transmit Operation
Figure 20.20 Transition Diagram between Operation Modes
bus inactive)
(waiting until
disabled
Module
(IDST = 1)
EN = 0
reset
configration
(after reset)
(IDST = 0)
Module
EN = 0
(IDST = 0)
EN = 1
(normal tx/rx)
enabled
Module
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