HD6417760BP200QS Renesas Electronics America, HD6417760BP200QS Datasheet - Page 89
HD6417760BP200QS
Manufacturer Part Number
HD6417760BP200QS
Description
IC SUPERH MCU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of HD6417760BP200QS
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
- Current page: 89 of 1418
- Download datasheet (9Mb)
Item
Cache memory
Interrupt controller
(INTC)
User break
controller (UBC)
Features
•
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Instruction cache (IC)
⎯ 16-Kbyte, 2-way set associative (LRU)
⎯ 256 entries, 32-byte block length
⎯ Cache-double-mode (16-Kbyte cache)
⎯ Index mode
Operand cache (OC)
⎯ 32-Kbyte, 2-way set associative (LRU)
⎯ 512 entries, 32-byte block length
⎯ Cache-double-mode (32-Kbyte cache)
⎯ Index mode
⎯ RAM mode (16-Kbyte cache + 16-Kbyte RAM)
⎯ Choice of write method (copy-back or write-through)
Single-stage copy-back buffer, single-stage write-through buffer
Cache memory contents can be accessed directly by address mapping
(usable as on-chip memory)
Store queue (32 bytes × 2 entries)
Nine independent external interrupts: NMI, IRL3 to IRL0, and IRQ7 to
IRQ4
15-level signed external interrupts: IRL3 to IRL0
On-chip peripheral module interrupts: Priority level can be set for each
module
Supports debugging by means of user break interrupts
Two break channels
Address, data value, access type, and data size can all be set as break
conditions
Supports sequential break function
Rev. 2.00 Feb. 12, 2010 Page 5 of 1330
REJ09B0554-0200
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