SAF-XC167CI-16F20F BB Infineon Technologies, SAF-XC167CI-16F20F BB Datasheet - Page 74
![no-image](/images/manufacturer_photos/0/3/327/infineon_technologies_sml.jpg)
SAF-XC167CI-16F20F BB
Manufacturer Part Number
SAF-XC167CI-16F20F BB
Description
IC MCU 16BIT 128KB TQFP-144-19
Manufacturer
Infineon Technologies
Series
XC16xr
Datasheet
1.SAF-XC167CI-16F20F_BB.pdf
(90 pages)
Specifications of SAF-XC167CI-16F20F BB
Core Processor
C166SV2
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
PWM, WDT
Number Of I /o
103
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.7 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFQFP
For Use With
B158-H8963-X-X-7600IN - KIT EASY XC167CIMCBX167-NET - BOARD EVAL INFINEON CAN/ETHRNTMCBXC167-BASIC - BOARD EVAL BASIC INFINEON XC16X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
FX167CI16F20FBBNP
FX167CI16F20FBBXP
SAFXC167CI16F20FBB
SP000094528
SP000224688
FX167CI16F20FBBXP
SAFXC167CI16F20FBB
SP000094528
SP000224688
4.4.2
The XC167’s Flash module delivers data within a fixed access time (see
Accesses to the Flash module are controlled by the PMI and take 1+WS clock cycles,
where WS is the number of Flash access waitstates selected via bitfield WSFLASH in
register IMBCTRL. The resulting duration of the access phase must cover the access
time
actual system frequency.
Note: The Flash access waitstates only affect non-sequential accesses. Due to
Table 17
Parameter
Flash module access time
Programming time per 128-byte block
Erase time per sector
1) Programming and erase time depends on the system frequency. Typical values are valid for 40 MHz.
Example: For an operating frequency of 40 MHz (clock cycle = 25 ns), devices can be
operated with 1 waitstate: ((1+1) × 25 ns) ≥ 50 ns.
Table 18
Table 18
Required Waitstates
0 WS (WSFLASH = 00
1 WS (WSFLASH = 01
Note: The maximum achievable system frequency is limited by the properties of the
Data Sheet
t
ACC
prefetching mechanisms, the performance for sequential accesses (depending on
the software structure) is only partially influenced by waitstates.
In typical applications, eliminating one waitstate increases the average
performance by 5% … 15%.
respective derivative, i.e. 40 MHz (or 20 MHz for xxx-16F20F devices).
indicates the interrelation of waitstates and system frequency.
of the Flash array. Therefore, the required Flash waitstates depend on the
On-chip Flash Operation
Flash Characteristics (Operating Conditions apply)
Flash Access Waitstates
B
B
)
)
72
Symbol
t
t
t
ACC
PR
ER
Frequency Range for
f
f
CPU
CPU
CC
CC
CC
≤ 20 MHz
≤ 40 MHz
Min.
–
–
–
Limit Values
Electrical Parameters
Typ.
2
–
200
1)
1)
XC167CI-16F
Max.
50
5
500
Table 17
Derivatives
V1.3, 2006-08
Unit
ns
ms
ms
).