AK5355VTP-E2 AKM Semiconductor Inc, AK5355VTP-E2 Datasheet - Page 11

• Manufacturer Part Number: AK5355VTP-E2
• Description: IC ADC AUDIO STER 16BIT 16TSSOP
• Manufacturer: AKM Semiconductor Inc
• Type: ADCr

Specifications of AK5355VTP-E2

• Resolution (bits): 16 b
• Sampling Rate (per Second): 44.1k
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Interface: -
• Other names: 974-1026-2; AK5355VTP

ASAHI KASEI
The AK5355 has a Digital High Pass Filter (HPF) to cancel DC-offset in both the ADC and input gain amplifier. The
cut-off frequency of the HPF is 3.4Hz at fs=44.1kHz. This cut-off frequency scales with the sampling frequency (fs).
The AK5355 includes an input gain amplifier. The gain can be changed to 0dB or +15dB by using the SEL pin. Input
impedance is 40kΩ typically.
The AK5355 is placed in the power-down mode by bringing PDN “L”. The digital filter is also reset at the same time. This
reset should always be done after power-up. An analog initialization cycle starts after exiting the power-down mode. The
output data SDTO becomes available after 4128 cycles of LRCK clock. During initialization, the ADC digital data
outputs of both channels are forced to a 2’s complement “0”. The ADC outputs settle to the data corresponding to the
input signals at the end of initialization (Settling time equals the group delay time approximately).
The AK5355 should be reset once by bringing PDN ”L” upon power-up. The AK5355 is powered up and the internal
timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK5355 is in the
power-down mode until MCLK and LRCK are input.
MS0113-E-01
Digital High Pass Filter
Input Gain Amplifier
Power down
System Reset
Notes:
Internal
A/D In
A/D Out
Clock In
MCLK,LRCK,BCLK
PDN
(Analog)
(Digital)
(1) Digital output corresponding to the analog input is delayed by the Group Delay amount (GD).
(2) A/D output is “0” data in the power-down state.
(3) When the external clocks (MCLK, BCLK and LRCK) are stopped, the AK5355 should be placed in the
State
power-down state.
Normal Operation
Idle Noise
GD
Figure 6. Power-down/up sequence example
(1)
Table 2. Input Gain Amplifier
SEL pin
(3)
Power-down
H
L
“0”data
(2)
- 11 -
4128/fs(93.6ms@fs=44.1kHz)
+15dB
Gain
0dB
Initialize
“0”data
Idle Noise
Normal Operation
GD
[AK5355]
2005/01