MC9S08AC32CPUE Freescale Semiconductor, MC9S08AC32CPUE Datasheet - Page 130

• Manufacturer Part Number: MC9S08AC32CPUE
• Description: IC MCU 8BIT 32K FLASH 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08AC32CPUE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Processor Series: S08AC
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 8 Cyclic Redundancy Check (S08CRCV1)
8.3
8.3.1
8.3.2
The CRC module includes:
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all CRC registers. This section refers to registers only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
8.3.2.1
130
CRCH
Field
(offset=0)
(offset=1)
Reset
7:0
CRCH
•
CRCL
Name
W
R
A 16-bit CRC result and seed register (CRCH:CRCL)
CRCH — This is the high byte of the 16-bit CRC register. A write to CRCH will load the high byte of the initial 16-bit
seed value directly into bits 15-8 of the shift register in the CRC generator. The CRC generator will then expect the
low byte of the seed value to be written to CRCL and loaded directly into bits 7-0 of the shift register. Once both seed
bytes written to CRCH:CRCL have been loaded into the CRC generator, and a byte of data has been written to
CRCL, the shift register will begin shifting. A read of CRCH will read bits 15-8 of the current CRC calculation result
directly out of the shift register in the CRC generator.
Register Definition
Bit 15
Memory Map
Register Descriptions
CRC High Register (CRCH)
0
7
W
W
R
R
Bit 15
Bit 7
7
Bit 14
0
6
Bit 14
Bit 6
6
Figure 8-3. CRC High Register (CRCH)
Table 8-2. Register Field Descriptions
MC9S08AC60 Series Data Sheet, Rev. 2
Table 8-1. CRC Register Summary
Bit 13
0
5
Bit 13
Bit 5
5
Bit 12
0
4
Description
Bit 12
Bit 4
4
Bit 11
3
0
Bit 11
Bit 3
3
Bit 10
0
2
Bit 10
Bit 2
2
Freescale Semiconductor
Bit 9
Bit 9
Bit 1
0
1
1
Bit 8
Bit 8
Bit 0
0
0
0