MCF5280CVM66 Freescale Semiconductor, MCF5280CVM66 Datasheet - Page 409

IC MPU 32BIT COLDF 256-MAPBGA

MCF5280CVM66

Manufacturer Part Number
MCF5280CVM66
Description
IC MPU 32BIT COLDF 256-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet

Specifications of MCF5280CVM66

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
142
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Controller Family/series
ColdFire
No. Of I/o's
150
Program Memory Size
2KB
Ram Memory Size
64KB
Cpu Speed
66.67MHz
Embedded Interface Type
CAN, I2C, SPI, UART
No. Of Pwm Channels
8
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Figure 22-3
22.3.2
The QDLYR is used to initiate master mode transfers and to set various delay parameters.
Freescale Semiconductor
IPSBAR
Field
14–8
QCD
Offset:
SPE
DTL
7–0
QSPI_DOUT
Reset
15
QSPI_CLK
QSPI_DIN
QSPI_CS
W
R
0x00_0344 (QDLYR)
QSPI enable. When set, the QSPI initiates transfers in master mode by executing commands in the command RAM.
The QSPI clears this bit automatically when a transfer completes. The user can also clear this bit to abort transfer
unless QIR[ABRTL] is set. The recommended method for aborting transfers is to set QWR[HALT].
QSPI_CLK delay. When the DSCK bit in the command RAM is set this field determines the length of the delay from
assertion of the chip selects to valid QSPI_CLK transition. See
setting this bit field.
Delay after transfer. When the DT bit in the command RAM is set this field determines the length of delay after the
serial transfer.
SPE
15
0
QSPI Delay Register (QDLYR)
shows an example of a QSPI clocking and data transfer.
14
0
QMR[CPOL] = 0
QMR[CPHA] = 1
QCR[CONT] = 0
msb
15
15
13
0
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
A
Figure 22-3. QSPI Clocking and Data Transfer Example
14
14
12
13
13
0
Figure 22-4. QSPI Delay Register (QDLYR)
Table 22-4. QDLYR Field Descriptions
QCD
12
12
11
0
11
11
10
1
10
10
9
9
0
9
Description
8
8
0
8
7
7
0
7
Section 22.4.3, “Transfer Delays”
6
6
Chip selects are active low
A = QDLYR[QCD]
B = QDLYR[DTL]
0
5
5
6
4
4
Queued Serial Peripheral Interface (QSPI)
0
5
3
3
0
4
DTL
2
2
0
3
1
1
Access: User read/write
0
0
for information on
1
2
B
0
1
22-5
0
0

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