MCF5280CVM66 Freescale Semiconductor, MCF5280CVM66 Datasheet - Page 490

• Manufacturer Part Number: MCF5280CVM66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5280CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• No. Of I/o's: 150
• Program Memory Size: 2KB
• Ram Memory Size: 64KB
• Cpu Speed: 66.67MHz
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

FlexCAN
25.5.2
Table 25-9
25-20
Bits
5–3
1–0
7
6
2
Address
Reset
Field BOFFMSK
ERRMSK
RXMODE
TXMODE
R/W
BOFFM-
FlexCAN Control Register 0 (CANCTRL0)
describes the CANCTRL0 fields.
Name
1
2
SK
—
TXMODE[1:0]
Full CMOS drive indicates that both dominant and recessive levels are driven by the chip.
Open drain drive indicates that only a dominant level is driven by the chip. During a recessive
level, the CANTX pin is disabled (three stated), and the electrical level is achieved by external
pull-up/pull-down devices. The assertion of both Tx mode bits causes the polarity inversion to be
cancelled (open drain mode forces the polarity to be positive).
1X
00
01
7
Bus off interrupt mask. The BOFF MASK bit provides a mask for the bus off interrupt.
0 Bus off interrupt disabled.
1 Bus off interrupt enabled.
Error interrupt mask. The ERRMSK bit provides a mask for the error interrupt.
0 Error interrupt disabled.
1 Error interrupt enabled.
Reserved
Receive pin configuration control. This bit determines the polarity of the CANRX pin.
0 A logical ‘0’ is interpreted as a dominant bit; a logical ‘1’ is interpreted as a recessive bit.
1 A logical ‘1’ is interpreted as a dominant bit; a logical ‘0’ is interpreted as a recessive bit.
Transmit pin configuration control. This bit field controls the configuration of the CANTX pin. See
Table
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
25-10.
Figure 25-7. FlexCAN Control Register 0 (CANCTRL0)
ERRMSK
Full CMOS
Full CMOS
Open drain
6
Table 25-9. CANCTRL0 Field Descriptions
Table 25-10. Transmit Pin Configuration
1
1
2
; positive polarity (CANTX= 0 is a dominant level)
; negative polarity (CANTX = 1 is a dominant level)
; positive polarity
5
Transmit Pin Configuration
IPSBAR + 0x1C_0006
—
4
0000_0000
Description
R/W
3
RXMODE
2
Freescale Semiconductor
1
TXMODE
0