MCIMX357DVM5B Freescale Semiconductor, MCIMX357DVM5B Datasheet - Page 65

• Manufacturer Part Number: MCIMX357DVM5B
• Description: PROCESSOR MULTIMEDIA 400PBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r

Specifications of MCIMX357DVM5B

• Core Processor: ARM11
• Core Size: 32-Bit
• Speed: 532MHz
• Connectivity: 1-Wire, CAN, EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 400-BGA
• Operating Temperature (min): -20C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 400
• Operating Temperature Range: -20°C To +70°C
• Processor Type: I.MX35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

1
2
3
4.9.11
This section describes the electrical characteristics of the I
4.9.11.1
Figure 44
Freescale Semiconductor
IC10 Rise time of both I2DAT and I2CLK signals
IC11 Fall time of both I2DAT and I2CLK signals
IC12 Capacitive load for each bus line (C
IC1
IC2
IC3
IC4
IC5
IC6
IC7
IC8
IC9
A device must internally provide a hold time of at least 300 ns for the I2DAT signal in order to bridge the undefined region of
the falling edge of I2CLK.
The maximum hold time has to be met only if the device does not stretch the LOW period (ID IC6) of the I2CLK signal.
A fast-mode I
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the I2CLK signal.
If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line
max_rise_time (ID No IC10) + data_setup_time (ID No IC8) = 1000 + 250 = 1250 ns (according to the Standard-mode I
specification) before the I2CLK line is released.
ID
I2CLK
I2DAT
I2CLK cycle time
Hold time (repeated) START condition
Set-up time for STOP condition
Data hold time
HIGH Period of I2CLK Clock
LOW Period of the I2CLK Clock
Set-up time for a repeated START condition
Data set-up time
Bus free time between a STOP and START condition
depicts the timing of the I
I
IC2
2
2
I
START
C-bus device can be used in a standard-mode I
C AC Electrical Specifications
2
C Module Timing
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
IC10
IC6
IC8
Parameter
IC1
IC10
Table 49. I
Figure 44. I
IC5
2
b
C module.
)
IC4
2
C Module Timing Parameters
2
IC11
C Bus Timing Diagram
Table 49
IC11
2
C-bus system, but the requirement of set-up time (ID IC7) of
lists the I
2
C module.
IC7
START
Standard Mode
Min.
250
4.0
4.0
4.0
4.7
4.7
4.7
10
0
—
—
—
1
2
C module timing parameters.
3.45
Max.
1000
300
400
—
—
—
—
—
—
—
—
2
IC3
STOP
Min.
100
Fast Mode
2.5
0.6
0.6
0.6
1.3
0.6
1.3
0
—
—
—
1
3
IC9
START
Max.
0.9
300
300
400
—
—
—
—
—
—
—
—
2
2
C-bus
Unit
μ s
μ s
μ s
μ s
μ s
μ s
μ s
ns
μ s
ns
ns
pF
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