MCF5272CVM66 Freescale Semiconductor, MCF5272CVM66 Datasheet - Page 237

• Manufacturer Part Number: MCF5272CVM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

The MII_SPEED field must be programmed with a value to provide an E_MDC frequency of less than or
equal to 2.5 MHz to be compliant with the IEEE MII specification. The MII_SPEED must be set to a
non-zero value in order to source a read or write management frame. After the management frame is
complete, the MSCR register may optionally be set to zero to turn off the E_MDC. The E_MDC generated
will have a 50% duty cycle except when MII_SPEED is changed during operation. Change will take effect
following either a rising or falling edge of E_MDC.
If the system clock is 50 MHz, programming this register to 0x0000_000A results in an E_MDC frequency
of 25 MHz * 1/10 = 2.5 MHz.
clock frequency.
11.5.9
FRBR is a read-only register used to determine the upper address boundary of the FIFO RAM. Drivers can
use this value, along with the registers FRSR and TFSR, to appropriately divide the available FIFO RAM
between the transmit and receive data paths. The value in this register must be added to MBAR + 0x800
to determine the absolute address.
Table 11-16
Freescale Semiconductor
31–11
10–2
Bits
1–0
Reset
Reset
R_BOUND
Field
Field
Addr
R/W
R/W
FIFO Receive Bound Register (FRBR)
describes the FRBR fields.
Name
—
—
System Clock Frequency
31
15
MCF5272 ColdFire
0000_0
Reserved, should be cleared.
End of FIFO RAM. This field contains the ending address of the FIFO RAM, exclusive.
Reserved, should be cleared.
25 MHz
33 MHz
50 MHz
66 MHz
—
Table 11-15. Programming Examples for MSCR Register
Figure 11-13. FIFO Receive Bound Register (FRBR)
Table 11-15
11
Table 11-16. FRBR Field Descriptions
10
®
Integrated Microprocessor User’s Manual, Rev. 3
shows optimum values for MII_SPEED as a function of system
0000_0000_0000_0000
[MII_SPEED]
MBAR + 0x884
0x5
0x3
0x4
0x7
Read only
Read only
110_0000_00
—
R_BOUND
Description
E_MDC frequency
2.08 MHz
2.06 MHz
2.36 MHz
2.5 MHz
2
1
00
—
Ethernet Module
16
0
11-19