MCF5272CVM66 Freescale Semiconductor, MCF5272CVM66 Datasheet - Page 324

• Manufacturer Part Number: MCF5272CVM66
• Description: IC MPU 66MHZ COLDFIRE 196-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5272CVM66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (4K x 32)
• Program Memory Type: ROM
• Ram Size: 1K x 32
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Cpu Speed: 66MHz
• Embedded Interface Type: UART, QSPI, USB, TDM
• Digital Ic Case Style: BGA
• No. Of Pins: 196
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Physical Layer Interface Controller (PLIC)
13.5.16 GCI C/I Channel Receive Registers (P0GCIR–P3GCIR)
All bits in these registers are read only and are cleared on hardware or software reset.
The PnGCIR registers contain the received C/I bits for one of each of the four ports on the MCF5272.
13-28
31–29, 23–21,
27–24, 19–16,
28, 20, 12, 4
15–13, 7–5
11–8, 3–0
Reset
Reset
Chan
Chan
Field
Field
Addr
R/W
R/W
Bits
31
15
C3–C0 C/I bits. These four bits are received on the GCI or SCIT channel 0. When a change in the C/I data
Name
—
—
—
Figure 13-28. GCI C/I Channel Receive Registers (P0GCIR–P3GCIR)
F
MCF5272 ColdFire
MBAR + 0x374 (P0GCIR), 0x375 (P1GCIR), 0x376 (P2GCIR), 0x377 (P3GCIR)
29
13
Reserved, should be cleared.
Full. This bit is set by the C/I channel controller to indicate to the CPU that new C/I channel data
has been received and is available for processing. It is automatically cleared by a CPU read. The
clearing of this bit by reading this register also clears the aperiodic GCR interrupt.
value is received in two successive frames, it is interpreted as being valid and is passed on to the
CPU, via this register. A maskable interrupt is generated when data is written into any of the four
available positions.
Table 13-11. P0GCIR–P3GCIR Field Descriptions
28
12
F
P0GCIR
F
P2GCIR
C3
C3
27
11
®
Integrated Microprocessor User’s Manual, Rev. 3
C2
C2
26
10
C1
0000_0000_0000_0000
C1
0000_0000_0000_0000
25
9
Read Only
Read Only
C0
C0
24
8
23
7
Description
—
—
21
5
20
F
P1GCIR
F
P3GCIR
4
C3
C3
19
3
Freescale Semiconductor
C2
C2
18
2
C1
C1
17
1
C0
C0
16
0