XR16C854IV-F Exar Corporation, XR16C854IV-F Datasheet - Page 14
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XR16C854IV-F
Manufacturer Part Number
XR16C854IV-F
Description
IC UART FIFO 128B QUAD 64LQFP
Manufacturer
Exar Corporation
Type
Quad UART with 128-byte FIFOsr
Datasheet
1.XR16C854IV-F.pdf
(54 pages)
Specifications of XR16C854IV-F
Number Of Channels
4, QUART
Package / Case
64-LQFP
Features
*
Fifo's
128 Byte
Protocol
RS232, RS485
Voltage - Supply
2.97 V ~ 5.5 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
2 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.97 V
Supply Current
3 mA to 6 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 45 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.97 V to 5.5 V
No. Of Channels
4
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
2.97V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
1016-1276
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR16C854IV-F
Manufacturer:
HYNIX
Quantity:
101
Company:
Part Number:
XR16C854IV-F
Manufacturer:
Exar Corporation
Quantity:
10 000
XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 128 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the TX FIFO and TSR are
reported in the Line Status Register (LSR bit-5 and bit-6).
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 128 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
O
2.11
2.11.1
2.11.2
UTPUT
MCR Bit-7=1
230.4k
115.2k
19.2k
38.4k
57.6k
1200
2400
4800
9600
100
600
Data Rate
Transmitter
Transmit Holding Register (THR) - Write Only
Transmitter Operation in non-FIFO Mode
F
T
IGURE
ABLE
XTAL1
XTAL2
O
UTPUT
6. B
6: T
MCR Bit-7=0
(D
153.6k
230.4k
460.8k
921.6k
EFAULT
19.2k
38.4k
76.8k
YPICAL DATA RATES WITH A
2400
4800
9600
AUD
400
Data Rate
R
Crystal
Buffer
)
Osc/
ATE
G
Clock (Decimal)
D
ENERATOR AND
IVISOR FOR
2304
384
192
96
48
24
12
6
4
2
1
Divide by 4
Divide by 1
Prescaler
Prescaler
16x
14.7456 MH
P
D
14
RESCALER
IVISOR FOR
Clock (HEX)
MCR Bit-7=0
MCR Bit-7=1
(default)
900
180
C0
0C
60
30
18
06
04
02
01
Z CRYSTAL OR EXTERNAL CLOCK
16x
Baud Rate
DLL and DLM
Generator
Registers
Logic
V
ALUE
P
ROGRAM
DLM
09
01
00
00
00
00
00
00
00
00
00
(HEX)
Rate Clock to
Transmitter
Sampling
V
16X
ALUE
P
ROGRAM
DLL
C0
0C
00
80
60
30
18
06
04
02
01
(HEX)
xr
D
E
REV. 3.0.1
ATA
RROR
0
0
0
0
0
0
0
0
0
0
0
R
ATE
(%)